Viability study of all-IIIV SRAM for beyond-22-nm logic circuits

A physics-based compact model for IIIV FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is optimized for maximum cell stability. The drawbacks of having a weak IIIV PMOS as the pull-up device in a SRAM cell are investigated. In this letter, we propose a minimum requirement for PMOS strength for all-IIIV SRAM to be viable in a logic chip. Also, by assuming a high-performance PMOS, we observe a 26% higher static current noise margin and a two times faster write speed compared to conventional SRAM.