Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device

Quanli Hu; Tae Kwang Eom; Soo Hyun Kim; Hyung Jun Kim; Hyun Ho Lee; Yong Sang Kim; Du Yeol Ryu; Ki Bum Kim; Tae Sik Yoon

doi:10.1149/1.3493685

Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device

Quanli Hu
, Tae Kwang Eom
, Soo Hyun Kim
, Hyung Jun Kim
, Hyun Ho Lee
, Yong Sang Kim
, Du Yeol Ryu
, Ki Bum Kim
, Tae Sik Yoon

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The formation of vertically and laterally self-aligned double-layer of CdSe colloidal nanocrystals (NCs) in nanopatterned dielectric layer on Si substrate was demonstrated by repeating dip-coating process for NC deposition and atomic layer deposition (ALD) of Al₂O₃ layer. A nanopatterned-SiO₂/Si substrate was formed by patterning with self-assembled diblock copolymer. After the selective deposition of the 1 ^st NC layer inside SiO₂ nanopattern by dip-coating, an Al₂O₃ interdielectric layer and the 2^nd NC layer in Al₂O₃ nanopattern were sequentially deposited. The capacitance-voltage measurement of Al-gate/ALD-Al₂O ₃(25nm)/2^nd-CdSe-NCs/ALD-Al₂O ₃(2nm)/1^st-CdSe-NCs/nanopatterned-Si0₂(15nm)/p- Si substrate structure showed the flatband voltage shift resulting from the charging of NCs.

Original language	English
Title of host publication	Low-Dimensional Nanoscale Electronic and Photonic Devices 4
Publisher	Electrochemical Society Inc.
Pages	75-82
Number of pages	8
Edition	9
ISBN (Electronic)	9781566778282
ISBN (Print)	9781607681786
DOIs	https://doi.org/10.1149/1.3493685
State	Published - 2010
Externally published	Yes
Event	Low-Dimensional Nanoscale Electronic and Photonic Devices 4 - 218th ECS Meeting - Las Vegas, NV, United States Duration: 10 Oct 2010 → 15 Oct 2010

Publication series

Name	ECS Transactions
Number	9
Volume	33
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	Low-Dimensional Nanoscale Electronic and Photonic Devices 4 - 218th ECS Meeting
Country/Territory	United States
City	Las Vegas, NV
Period	10/10/10 → 15/10/10

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10.1149/1.3493685

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Hu, Q., Eom, T. K., Kim, S. H., Kim, H. J., Lee, H. H., Kim, Y. S., Ryu, D. Y., Kim, K. B., & Yoon, T. S. (2010). Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device. In Low-Dimensional Nanoscale Electronic and Photonic Devices 4 (9 ed., pp. 75-82). (ECS Transactions; Vol. 33, No. 9). Electrochemical Society Inc.. https://doi.org/10.1149/1.3493685

@inproceedings{0c706a33fae54054a7afc43a62af83a2,

title = "Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device",

abstract = "The formation of vertically and laterally self-aligned double-layer of CdSe colloidal nanocrystals (NCs) in nanopatterned dielectric layer on Si substrate was demonstrated by repeating dip-coating process for NC deposition and atomic layer deposition (ALD) of Al2O3 layer. A nanopatterned-SiO2/Si substrate was formed by patterning with self-assembled diblock copolymer. After the selective deposition of the 1 st NC layer inside SiO2 nanopattern by dip-coating, an Al2O3 interdielectric layer and the 2nd NC layer in Al2O3 nanopattern were sequentially deposited. The capacitance-voltage measurement of Al-gate/ALD-Al2O 3(25nm)/2nd-CdSe-NCs/ALD-Al2O 3(2nm)/1st-CdSe-NCs/nanopatterned-Si02(15nm)/p- Si substrate structure showed the flatband voltage shift resulting from the charging of NCs.",

author = "Quanli Hu and Eom, \{Tae Kwang\} and Kim, \{Soo Hyun\} and Kim, \{Hyung Jun\} and Lee, \{Hyun Ho\} and Kim, \{Yong Sang\} and Ryu, \{Du Yeol\} and Kim, \{Ki Bum\} and Yoon, \{Tae Sik\}",

year = "2010",

doi = "10.1149/1.3493685",

language = "English",

isbn = "9781607681786",

series = "ECS Transactions",

publisher = "Electrochemical Society Inc.",

number = "9",

pages = "75--82",

booktitle = "Low-Dimensional Nanoscale Electronic and Photonic Devices 4",

edition = "9",

note = "Low-Dimensional Nanoscale Electronic and Photonic Devices 4 - 218th ECS Meeting ; Conference date: 10-10-2010 Through 15-10-2010",

}

Hu, Q, Eom, TK, Kim, SH, Kim, HJ, Lee, HH, Kim, YS, Ryu, DY, Kim, KB & Yoon, TS 2010, Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device. in Low-Dimensional Nanoscale Electronic and Photonic Devices 4. 9 edn, ECS Transactions, no. 9, vol. 33, Electrochemical Society Inc., pp. 75-82, Low-Dimensional Nanoscale Electronic and Photonic Devices 4 - 218th ECS Meeting, Las Vegas, NV, United States, 10/10/10. https://doi.org/10.1149/1.3493685

Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device. / Hu, Quanli; Eom, Tae Kwang; Kim, Soo Hyun et al.
Low-Dimensional Nanoscale Electronic and Photonic Devices 4. 9. ed. Electrochemical Society Inc., 2010. p. 75-82 (ECS Transactions; Vol. 33, No. 9).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device

AU - Hu, Quanli

AU - Eom, Tae Kwang

AU - Kim, Soo Hyun

AU - Kim, Hyung Jun

AU - Lee, Hyun Ho

AU - Kim, Yong Sang

AU - Ryu, Du Yeol

AU - Kim, Ki Bum

AU - Yoon, Tae Sik

PY - 2010

Y1 - 2010

N2 - The formation of vertically and laterally self-aligned double-layer of CdSe colloidal nanocrystals (NCs) in nanopatterned dielectric layer on Si substrate was demonstrated by repeating dip-coating process for NC deposition and atomic layer deposition (ALD) of Al2O3 layer. A nanopatterned-SiO2/Si substrate was formed by patterning with self-assembled diblock copolymer. After the selective deposition of the 1 st NC layer inside SiO2 nanopattern by dip-coating, an Al2O3 interdielectric layer and the 2nd NC layer in Al2O3 nanopattern were sequentially deposited. The capacitance-voltage measurement of Al-gate/ALD-Al2O 3(25nm)/2nd-CdSe-NCs/ALD-Al2O 3(2nm)/1st-CdSe-NCs/nanopatterned-Si02(15nm)/p- Si substrate structure showed the flatband voltage shift resulting from the charging of NCs.

AB - The formation of vertically and laterally self-aligned double-layer of CdSe colloidal nanocrystals (NCs) in nanopatterned dielectric layer on Si substrate was demonstrated by repeating dip-coating process for NC deposition and atomic layer deposition (ALD) of Al2O3 layer. A nanopatterned-SiO2/Si substrate was formed by patterning with self-assembled diblock copolymer. After the selective deposition of the 1 st NC layer inside SiO2 nanopattern by dip-coating, an Al2O3 interdielectric layer and the 2nd NC layer in Al2O3 nanopattern were sequentially deposited. The capacitance-voltage measurement of Al-gate/ALD-Al2O 3(25nm)/2nd-CdSe-NCs/ALD-Al2O 3(2nm)/1st-CdSe-NCs/nanopatterned-Si02(15nm)/p- Si substrate structure showed the flatband voltage shift resulting from the charging of NCs.

UR - https://www.scopus.com/pages/publications/84863137771

U2 - 10.1149/1.3493685

DO - 10.1149/1.3493685

M3 - Conference contribution

AN - SCOPUS:84863137771

SN - 9781607681786

T3 - ECS Transactions

SP - 75

EP - 82

BT - Low-Dimensional Nanoscale Electronic and Photonic Devices 4

PB - Electrochemical Society Inc.

T2 - Low-Dimensional Nanoscale Electronic and Photonic Devices 4 - 218th ECS Meeting

Y2 - 10 October 2010 through 15 October 2010

ER -

Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device

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