Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature

This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion}/Ioff ratio (\∼ 10⁵), as well as low Drain-Induced Barrier Lowering of ∼70 mV/V.