Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application

Joong Sik Kim; Sung Woong Chung; Tae Su Jang; Seung Hwan Lee; Dong Hee Son; Seoung Ju Chung; Sang Min Hwang; Srinivasa Banna; Sunil Bhardwaj; Mayank Gupta; Jungtae Kwon; David Kim; Greg Popov; Venkatesh Gopinath; Michael Van Buskirk; Sang Hoon Cho; Jae Sung Roh; Sung Joo Hong; Sung Wook Park

doi:10.1109/VLSIT.2010.5556212

Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application

Joong Sik Kim, Sung Woong Chung, Tae Su Jang, Seung Hwan Lee, Dong Hee Son, Seoung Ju Chung, Sang Min Hwang, Srinivasa Banna, Sunil Bhardwaj, Mayank Gupta, Jungtae Kwon, David Kim, Greg Popov, Venkatesh Gopinath, Michael Van Buskirk, Sang Hoon Cho, Jae Sung Roh, Sung Joo Hong, Sung Wook Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000x improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date. keywords: ZRAM, floating body cell, 1T-DRAM.

Original language	English
Title of host publication	2010 Symposium on VLSI Technology, VLSIT 2010
Pages	163-164
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2010.5556212
State	Published - 2010
Externally published	Yes
Event	2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States Duration: 15 Jun 2010 → 17 Jun 2010

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	2010 Symposium on VLSI Technology, VLSIT 2010
Country/Territory	United States
City	Honolulu, HI
Period	15/06/10 → 17/06/10

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10.1109/VLSIT.2010.5556212

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Kim, J. S., Chung, S. W., Jang, T. S., Lee, S. H., Son, D. H., Chung, S. J., Hwang, S. M., Banna, S., Bhardwaj, S., Gupta, M., Kwon, J., Kim, D., Popov, G., Gopinath, V., Buskirk, M. V., Cho, S. H., Roh, J. S., Hong, S. J., & Park, S. W. (2010). Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application. In 2010 Symposium on VLSI Technology, VLSIT 2010 (pp. 163-164). Article 5556212 (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2010.5556212

@inproceedings{e3c9f307f4074d5cb00fd2baf17d4b6c,

title = "Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application",

abstract = "Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000x improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date. keywords: ZRAM, floating body cell, 1T-DRAM.",

author = "Kim, \{Joong Sik\} and Chung, \{Sung Woong\} and Jang, \{Tae Su\} and Lee, \{Seung Hwan\} and Son, \{Dong Hee\} and Chung, \{Seoung Ju\} and Hwang, \{Sang Min\} and Srinivasa Banna and Sunil Bhardwaj and Mayank Gupta and Jungtae Kwon and David Kim and Greg Popov and Venkatesh Gopinath and Buskirk, \{Michael Van\} and Cho, \{Sang Hoon\} and Roh, \{Jae Sung\} and Hong, \{Sung Joo\} and Park, \{Sung Wook\}",

year = "2010",

doi = "10.1109/VLSIT.2010.5556212",

language = "English",

isbn = "9781424476374",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "163--164",

booktitle = "2010 Symposium on VLSI Technology, VLSIT 2010",

note = "2010 Symposium on VLSI Technology, VLSIT 2010 ; Conference date: 15-06-2010 Through 17-06-2010",

}

Kim, JS, Chung, SW, Jang, TS, Lee, SH, Son, DH, Chung, SJ, Hwang, SM, Banna, S, Bhardwaj, S, Gupta, M, Kwon, J, Kim, D, Popov, G, Gopinath, V, Buskirk, MV, Cho, SH, Roh, JS, Hong, SJ & Park, SW 2010, Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application. in 2010 Symposium on VLSI Technology, VLSIT 2010., 5556212, Digest of Technical Papers - Symposium on VLSI Technology, pp. 163-164, 2010 Symposium on VLSI Technology, VLSIT 2010, Honolulu, HI, United States, 15/06/10. https://doi.org/10.1109/VLSIT.2010.5556212

Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application. / Kim, Joong Sik; Chung, Sung Woong; Jang, Tae Su et al.
2010 Symposium on VLSI Technology, VLSIT 2010. 2010. p. 163-164 5556212 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application

AU - Kim, Joong Sik

AU - Chung, Sung Woong

AU - Jang, Tae Su

AU - Lee, Seung Hwan

AU - Son, Dong Hee

AU - Chung, Seoung Ju

AU - Hwang, Sang Min

AU - Banna, Srinivasa

AU - Bhardwaj, Sunil

AU - Gupta, Mayank

AU - Kwon, Jungtae

AU - Kim, David

AU - Popov, Greg

AU - Gopinath, Venkatesh

AU - Buskirk, Michael Van

AU - Cho, Sang Hoon

AU - Roh, Jae Sung

AU - Hong, Sung Joo

AU - Park, Sung Wook

PY - 2010

Y1 - 2010

N2 - Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000x improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date. keywords: ZRAM, floating body cell, 1T-DRAM.

AB - Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000x improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date. keywords: ZRAM, floating body cell, 1T-DRAM.

UR - https://www.scopus.com/pages/publications/77957859015

U2 - 10.1109/VLSIT.2010.5556212

DO - 10.1109/VLSIT.2010.5556212

M3 - Conference contribution

AN - SCOPUS:77957859015

SN - 9781424476374

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 163

EP - 164

BT - 2010 Symposium on VLSI Technology, VLSIT 2010

T2 - 2010 Symposium on VLSI Technology, VLSIT 2010

Y2 - 15 June 2010 through 17 June 2010

ER -

Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application

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