Ultra high frequency static dividers in a narrow mesa InGaAs/InP DHBT technology

Z. Griffith; M. Dahlström; M. Seo; M. J.W. Rodwell; M. Urteaga; R. Pierson; P. Rowell; B. Brar; S. Lee; N. Nguyen; C. Nguyen

Ultra high frequency static dividers in a narrow mesa InGaAs/InP DHBT technology

Z. Griffith
, M. Dahlström
, M. Seo
, M. J.W. Rodwell
, M. Urteaga
, R. Pierson
, P. Rowell
, B. Brar
, S. Lee
, N. Nguyen
, C. Nguyen

Research output: Contribution to journal › Conference article › peer-review

Abstract

Static frequency dividers with a maximum clock frequency > 110 GHz were designed and fabricated in a narrow mesa InP/In_0.53Ga _0.47As/InP DHBT technology. Divider operation is fully static, operating from f_clk = 4 GHz to 118.70 GHz and dissipating 686.4 mW of power from a -4.2 Volt supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 μm and a collector-to-emitter area ratio of 3.0. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies > 100 GHz.

Original language	English
Pages (from-to)	663-666
Number of pages	4
Journal	Conference Proceedings - International Conference on Indium Phosphide and Related Materials
State	Published - 2004
Externally published	Yes
Event	2004 International Conference on Indium Phosphide and Related Materials, 16th IPRM - Kagoshima, Japan Duration: 31 May 2004 → 4 Jun 2004

Cite this

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title = "Ultra high frequency static dividers in a narrow mesa InGaAs/InP DHBT technology",

abstract = "Static frequency dividers with a maximum clock frequency > 110 GHz were designed and fabricated in a narrow mesa InP/In0.53Ga 0.47As/InP DHBT technology. Divider operation is fully static, operating from fclk = 4 GHz to 118.70 GHz and dissipating 686.4 mW of power from a -4.2 Volt supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 μm and a collector-to-emitter area ratio of 3.0. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies > 100 GHz.",

author = "Z. Griffith and M. Dahlstr{\"o}m and M. Seo and Rodwell, \{M. J.W.\} and M. Urteaga and R. Pierson and P. Rowell and B. Brar and S. Lee and N. Nguyen and C. Nguyen",

year = "2004",

language = "English",

pages = "663--666",

journal = "Conference Proceedings - International Conference on Indium Phosphide and Related Materials",

issn = "1092-8669",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 International Conference on Indium Phosphide and Related Materials, 16th IPRM ; Conference date: 31-05-2004 Through 04-06-2004",

}

TY - JOUR

T1 - Ultra high frequency static dividers in a narrow mesa InGaAs/InP DHBT technology

AU - Griffith, Z.

AU - Dahlström, M.

AU - Seo, M.

AU - Rodwell, M. J.W.

AU - Urteaga, M.

AU - Pierson, R.

AU - Rowell, P.

AU - Brar, B.

AU - Lee, S.

AU - Nguyen, N.

AU - Nguyen, C.

PY - 2004

Y1 - 2004

N2 - Static frequency dividers with a maximum clock frequency > 110 GHz were designed and fabricated in a narrow mesa InP/In0.53Ga 0.47As/InP DHBT technology. Divider operation is fully static, operating from fclk = 4 GHz to 118.70 GHz and dissipating 686.4 mW of power from a -4.2 Volt supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 μm and a collector-to-emitter area ratio of 3.0. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies > 100 GHz.

AB - Static frequency dividers with a maximum clock frequency > 110 GHz were designed and fabricated in a narrow mesa InP/In0.53Ga 0.47As/InP DHBT technology. Divider operation is fully static, operating from fclk = 4 GHz to 118.70 GHz and dissipating 686.4 mW of power from a -4.2 Volt supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 μm and a collector-to-emitter area ratio of 3.0. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies > 100 GHz.

UR - https://www.scopus.com/pages/publications/17044433906

M3 - Conference article

AN - SCOPUS:17044433906

SN - 1092-8669

SP - 663

EP - 666

JO - Conference Proceedings - International Conference on Indium Phosphide and Related Materials

JF - Conference Proceedings - International Conference on Indium Phosphide and Related Materials

T2 - 2004 International Conference on Indium Phosphide and Related Materials, 16th IPRM

Y2 - 31 May 2004 through 4 June 2004

ER -

Ultra high frequency static dividers in a narrow mesa InGaAs/InP DHBT technology

Abstract

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