True single-phase clocking scheme for low-power and high-speed VLSI

This paper describes a true-single-phase clocking scheme with charge-recycling differential logic (CRDL). The original CRDL circuit is modified for use with only a single-phase clock signal which is never inverted. This circuit achieves low-power and high-speed operation by eliminating the need for slow PMOS-logic blocks in a pipelined configuration, in addition to using charge-recycling technique. XOR/XNOR gates and a pipelined 32-bit adder are constructed with this circuit technique. The simulation results show that the proposed clocking scheme improves power-delay product by 30.1 to 49.8% as compared to the true-single-phase clocking scheme with conventional differential cascode voltage switch (DCVS) logic.