Time-step interleaved weight reuse for LSTM neural network computing

  • Naebeom Park
  • , Yulhwa Kim
  • , Daehyun Ahn
  • , Taesu Kim
  • , Jae Joon Kim

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In Long Short-Term Memory (LSTM) neural network models, a weight matrix tends to be repeatedly loaded from DRAM if the size of on-chip storage of the processor is not large enough to store the entire matrix. To alleviate heavy overhead of DRAM access for weight loading in LSTM computations, we propose a weight reuse scheme which utilizes the weight sharing characteristics in two adjacent time-step computations. Experimental results show that the proposed weight reuse scheme reduces the energy consumption by 28.4-57.3% and increases the overall throughput by 110.8% compared to the conventional schemes.

Original languageEnglish
Title of host publicationProceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020
PublisherAssociation for Computing Machinery
ISBN (Electronic)9781450370530
DOIs
StatePublished - 10 Aug 2020
Externally publishedYes
Event2020 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020 - Virtual, Online, United States
Duration: 10 Aug 202012 Aug 2020

Publication series

NameACM International Conference Proceeding Series

Conference

Conference2020 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020
Country/TerritoryUnited States
CityVirtual, Online
Period10/08/2012/08/20

Keywords

  • long short-Term memory
  • weight reuse

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