TY - GEN
T1 - The phoenix processor
T2 - 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
AU - Seok, Mingoo
AU - Hanson, Scott
AU - Lin, Yu Shiang
AU - Foo, Zhiyoong
AU - Kim, Daeyeon
AU - Lee, Yoonmyung
AU - Liu, Nurrachman
AU - Sylvester, Dennis
AU - Blaauw, David
PY - 2008
Y1 - 2008
N2 - An integrated platform for sensor applications, called the Phoenix Processor, is implemented in a carefully-selected 0.18μm process with an area of 915x915μm2, making on-die battery integration feasible. Phoenix uses a comprehensive sleep strategy with a unique power gating approach, an event-driven CPU with compact ISA, data memory compression, a custom low leakage memory cell, and adaptive leakage management in data memory. Measurements show that Phoenix consumes 29.6pW in sleep mode and 2.8pJ/cycle in active mode.
AB - An integrated platform for sensor applications, called the Phoenix Processor, is implemented in a carefully-selected 0.18μm process with an area of 915x915μm2, making on-die battery integration feasible. Phoenix uses a comprehensive sleep strategy with a unique power gating approach, an event-driven CPU with compact ISA, data memory compression, a custom low leakage memory cell, and adaptive leakage management in data memory. Measurements show that Phoenix consumes 29.6pW in sleep mode and 2.8pJ/cycle in active mode.
UR - https://www.scopus.com/pages/publications/51949107763
U2 - 10.1109/VLSIC.2008.4586001
DO - 10.1109/VLSIC.2008.4586001
M3 - Conference contribution
AN - SCOPUS:51949107763
SN - 9781424418053
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 188
EP - 189
BT - 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 18 June 2008 through 20 June 2008
ER -