The design and signal integrity analysis of a TB/sec memory system

The design and signal integrity analysis of a Terabyte per second (TB/sec) memory system is presented in this work. The interface technology utilizes a bi-directional low-swing differential signaling with a data transfer rate of 16 Gbps/pair. The memory system uses asymmetrical architecture where the timing adjustment and equalization circuits for both memory WRITE and READ are placed on the controller to reduce the power and cost of the system. This paper describes the design and analysis employed to develop highspeed memory interface using low-cost interconnect technologies. The characterization and model to hardware correlations of the prototype system at component and system-level are also presented. System analysis is used to optimize and predict the yield of the system, to calculate system timing and voltage margins, and to verify targeted bit-error-rate (BER).