Technology projection using simple compact models

  • H. S.Philip Wong
  • , Lan Wei
  • , Saeroonter Oh
  • , Albert Lin
  • , Jie Deng
  • , Soogine Chong
  • , Kerem Akarvardar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

We review recent efforts to capture the device non-idealities for circuit-level technology projection for Si CMOS. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V FET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.

Original languageEnglish
Title of host publicationSISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices
DOIs
StatePublished - 2009
Externally publishedYes
EventSISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices - San Diego, CA, United States
Duration: 9 Sep 200911 Sep 2009

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

ConferenceSISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices
Country/TerritoryUnited States
CitySan Diego, CA
Period9/09/0911/09/09

Keywords

  • Carbon nanotube transistor
  • CNT
  • Compact model
  • III-V FET
  • Nanoelectromechanical relay
  • NEMS
  • Parasitic capacitance
  • Parasitic resistance
  • Si CMOS
  • Technology projection

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