@inproceedings{d62cc9292f244e83bcadd9cc00551a81,
title = "Technology projection using simple compact models",
abstract = "We review recent efforts to capture the device non-idealities for circuit-level technology projection for Si CMOS. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V FET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.",
keywords = "Carbon nanotube transistor, CNT, Compact model, III-V FET, Nanoelectromechanical relay, NEMS, Parasitic capacitance, Parasitic resistance, Si CMOS, Technology projection",
author = "Wong, \{H. S.Philip\} and Lan Wei and Saeroonter Oh and Albert Lin and Jie Deng and Soogine Chong and Kerem Akarvardar",
year = "2009",
doi = "10.1109/SISPAD.2009.5290261",
language = "English",
isbn = "9781424439492",
series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",
booktitle = "SISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices",
note = "SISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices ; Conference date: 09-09-2009 Through 11-09-2009",
}