Suppression of the Floating-Body Effect of Vertical-Cell DRAM with the Buried Body Engineering Method

Recently, new dynamic random-access memory (DRAM) structures have been used to sharply reduce chip size. One of these is vertical-cell DRAM that has the advantage of reducing the chip area by 33% compared with the conventional cell DRAM. However, since the bitline is made in Si trenches, it can cause a floating-body effect, which increases the OFF current. Here, we suggest the buried body engineering method as a simple way to deal with these disadvantages without changing the materials. This method significantly improved the electrical performance in comparison with the conventional buried contact. Especially, the OFF current, which is the most important factor influencing the refresh time, was dramatically reduced by a factor of 63. The reason for this dramatic decrease in the OFF current is that the holes accumulated in the body are removed immediately, and they do not generate a parasitic bipolar junction transistor (BJT) action. We also calculated the hole density using simulations and obtained the junction depth that suppresses the floating-body effect. Above all, we provide advanced insight into the mechanism of the parasitic BJT action due to the floating-body effect that occurs at the bottom contact region of vertical-cell DRAM.