Strain effectiveness of gate-all-around silicon transistors with various surface orientations and cross-sections

We investigate the effect of strain on the device characteristics of gate-all-around (GAA) NMOS with various configurations, including crystal orientation, cross-sectional shape, and strain conditions, via device simulation. After verifying the strain dependence of mobility of various surface orientations with the literature, we apply the strain transport model to GAA MOSFETs which have different sidewall orientations depending on the channel direction. Drive current enhancement is the largest for the (001)/<110> case under large uniaxial tensile strain values exceeding 1%. In addition, we found that cross-sectional width of the nanosheet is a key parameter in maximizing the drive current for a given footprint. Optimization of device and strain configuration of single-stacked GAA devices is necessary to meet device performance specifications for sub-7nm technology.