Standby power reduction techniques for ultra-low power processors

Yoonmyung Lee; Mingoo Seok; Scott Hanson; David Blaauw; Dennis Sylvester

doi:10.1109/ESSCIRC.2008.4681823

Standby power reduction techniques for ultra-low power processors

Yoonmyung Lee
, Mingoo Seok
, Scott Hanson
, David Blaauw
, Dennis Sylvester

University of Michigan, Ann Arbor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

Standby power can dominate the power budgets of battery-operated ultra-low power processors, and reducing standby power is the key challenge for further power reduction. State-of-the-art ultra low voltage sensors consume hundreds of nW in wake mode and 100 pW or less in standby mode. Therefore, applying known circuit techniques for further standby power reduction is very challenging. In this paper, we extend known standby power reduction techniques for use in ultra-low power processors. In particular, we propose structures that enable the use of super cut-off voltages throughout the design with minimal power overhead. Different strategies for power gated logic blocks and memory cells are investigated.

Original language	English
Title of host publication	ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
Pages	186-189
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2008.4681823
State	Published - 2008
Externally published	Yes
Event	34th European Solid-State Circuits Conference, ESSCIRC 2008 - Edinburgh, Scotland, United Kingdom Duration: 15 Sep 2008 → 19 Sep 2008

Publication series

Name	ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Conference

Conference	34th European Solid-State Circuits Conference, ESSCIRC 2008
Country/Territory	United Kingdom
City	Edinburgh, Scotland
Period	15/09/08 → 19/09/08

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10.1109/ESSCIRC.2008.4681823

Cite this

Lee, Y., Seok, M., Hanson, S., Blaauw, D., & Sylvester, D. (2008). Standby power reduction techniques for ultra-low power processors. In ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference (pp. 186-189). Article 4681823 (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2008.4681823

@inproceedings{56c0b6c4cb1844efb8332d3810635dbe,

title = "Standby power reduction techniques for ultra-low power processors",

abstract = "Standby power can dominate the power budgets of battery-operated ultra-low power processors, and reducing standby power is the key challenge for further power reduction. State-of-the-art ultra low voltage sensors consume hundreds of nW in wake mode and 100 pW or less in standby mode. Therefore, applying known circuit techniques for further standby power reduction is very challenging. In this paper, we extend known standby power reduction techniques for use in ultra-low power processors. In particular, we propose structures that enable the use of super cut-off voltages throughout the design with minimal power overhead. Different strategies for power gated logic blocks and memory cells are investigated.",

author = "Yoonmyung Lee and Mingoo Seok and Scott Hanson and David Blaauw and Dennis Sylvester",

year = "2008",

doi = "10.1109/ESSCIRC.2008.4681823",

language = "English",

isbn = "9781424423620",

series = "ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference",

pages = "186--189",

booktitle = "ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference",

note = "34th European Solid-State Circuits Conference, ESSCIRC 2008 ; Conference date: 15-09-2008 Through 19-09-2008",

}

Lee, Y, Seok, M, Hanson, S, Blaauw, D & Sylvester, D 2008, Standby power reduction techniques for ultra-low power processors. in ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference., 4681823, ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, pp. 186-189, 34th European Solid-State Circuits Conference, ESSCIRC 2008, Edinburgh, Scotland, United Kingdom, 15/09/08. https://doi.org/10.1109/ESSCIRC.2008.4681823

Standby power reduction techniques for ultra-low power processors. / Lee, Yoonmyung; Seok, Mingoo; Hanson, Scott et al.
ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference. 2008. p. 186-189 4681823 (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Standby power reduction techniques for ultra-low power processors

AU - Lee, Yoonmyung

AU - Seok, Mingoo

AU - Hanson, Scott

AU - Blaauw, David

AU - Sylvester, Dennis

PY - 2008

Y1 - 2008

N2 - Standby power can dominate the power budgets of battery-operated ultra-low power processors, and reducing standby power is the key challenge for further power reduction. State-of-the-art ultra low voltage sensors consume hundreds of nW in wake mode and 100 pW or less in standby mode. Therefore, applying known circuit techniques for further standby power reduction is very challenging. In this paper, we extend known standby power reduction techniques for use in ultra-low power processors. In particular, we propose structures that enable the use of super cut-off voltages throughout the design with minimal power overhead. Different strategies for power gated logic blocks and memory cells are investigated.

AB - Standby power can dominate the power budgets of battery-operated ultra-low power processors, and reducing standby power is the key challenge for further power reduction. State-of-the-art ultra low voltage sensors consume hundreds of nW in wake mode and 100 pW or less in standby mode. Therefore, applying known circuit techniques for further standby power reduction is very challenging. In this paper, we extend known standby power reduction techniques for use in ultra-low power processors. In particular, we propose structures that enable the use of super cut-off voltages throughout the design with minimal power overhead. Different strategies for power gated logic blocks and memory cells are investigated.

UR - https://www.scopus.com/pages/publications/58049118870

U2 - 10.1109/ESSCIRC.2008.4681823

DO - 10.1109/ESSCIRC.2008.4681823

M3 - Conference contribution

AN - SCOPUS:58049118870

SN - 9781424423620

T3 - ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

SP - 186

EP - 189

BT - ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

T2 - 34th European Solid-State Circuits Conference, ESSCIRC 2008

Y2 - 15 September 2008 through 19 September 2008

ER -

Standby power reduction techniques for ultra-low power processors

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