SRAM bitcell Design and Characteristics in the three-stacked CFET structure for CMOS scaling

In this study, a novel three-stacked CFET SRAM structure is proposed, achieving a 27% improvement in area scaling compared to conventional two-stacked CFET SRAM architectures. Through comprehensive 3D TCAD simulations and a BSIM-CMG-based compact model, a detailed analysis of resistance and capacitance characteristics is conducted to evaluate the performance and stability of the proposed design. The three-stacked configuration effectively minimizes the footprint, resulting in a 1.6x increase in BL capacitance due to reduced metal pitch, leading to AC performance degradation. However, despite a 1.2x difference in BL resistance, SNM and WRM show no difference compared to the conventional design. To fully leverage the advantage of enhanced area scaling while addressing the AC performance limitations, it is recommended to explore the use of low-resistance metals to improve write-ability, or to redesign the metal line structure to achieve a better balance between resistance and capacitance. These design enhancements effectively maintain the area scaling advantage while improving the stability margin. The insights gained from this work provide a valuable foundation for enabling continued scaling in future logic technology nodes.