TY - GEN
T1 - SOI design for a high-performance IO interface
AU - Chang, Ken
AU - Wu, Ting
AU - Kaviani, Kambiz
AU - Chun, Jung Hoon
PY - 2009
Y1 - 2009
N2 - SOI technology is well suited for high speed digital circuits. However, its history effect due to the floating body poses a major challenge to analog circuits. This paper presents the design of a high-performance IO interface (FlexIO™ [5]) used in Cell Broadband Engine™ processors [1][4], currently in mass production. The design has been scaled across 90nm, 65nm, and 45nm SOI CMOS processes. The parallel interface implemented in 45nm SOI comprises 5 transmit and 5 receive bytes with each link unidirectionally running at 6.4Gb/s achieving BER < 10-20. The paper discusses clocking, IO, and ESD aspects of the design in SOI processes.
AB - SOI technology is well suited for high speed digital circuits. However, its history effect due to the floating body poses a major challenge to analog circuits. This paper presents the design of a high-performance IO interface (FlexIO™ [5]) used in Cell Broadband Engine™ processors [1][4], currently in mass production. The design has been scaled across 90nm, 65nm, and 45nm SOI CMOS processes. The parallel interface implemented in 45nm SOI comprises 5 transmit and 5 receive bytes with each link unidirectionally running at 6.4Gb/s achieving BER < 10-20. The paper discusses clocking, IO, and ESD aspects of the design in SOI processes.
UR - https://www.scopus.com/pages/publications/72449199063
U2 - 10.1109/SOI.2009.5318762
DO - 10.1109/SOI.2009.5318762
M3 - Conference contribution
AN - SCOPUS:72449199063
SN - 9781424452323
T3 - Proceedings - IEEE International SOI Conference
BT - 2009 IEEE International SOI Conference
T2 - 2009 IEEE International SOI Conference
Y2 - 5 October 2009 through 8 October 2009
ER -