Schottky-barrier si nanowire mosfet: Effects of source/drain metals and gate dielectrics

Weifeng Yang, Sungjin Whang, Sungjoo Lee, Haichen Zhu, Hanlu Gu, Byungjin Cho

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

We fabricated and studied the performance of Schottky-Barrier Si nanowire FETs (SiNW FET) by using Vapor-liquid-solid (VLS) grown Au-catalyzed SiNWs (20 nm). These devices were formed on various gate dielectrics (Hf02 or A1203) with different metal Source and Drain (S/D) regions (Pd, Ni). P-type behavior was observed and high Ion/Iof ratio (-10-5) was achieved from undoped SiNW FETs. Besides, no ambipolar transportation was observed in our devices performance. This is possibly due to the small schottky barrier height for hole carriers at Source sides formed by high work-function metal. Furthermore, low subthreshold slope as 68mV/decade was obtained from SiNW FETs integrated with Ni S/D and A1203 High-K gate dielectric.

Original languageEnglish
Title of host publicationMaterials Research Society Symposium Proceedings - Low-Dimensional Materials- Synthesis, Assembly, Property Scaling, and Modeling
PublisherMaterials Research Society
Pages133-138
Number of pages6
ISBN (Print)9781605604237
DOIs
StatePublished - 2007
Externally publishedYes
EventLow-Dimensional Materials- Synthesis, Assembly, Property Scaling, and Modeling - 2007 MRS Spring Meeting - San Francisco, CA, United States
Duration: 9 Apr 200713 Apr 2007

Publication series

NameMaterials Research Society Symposium Proceedings
Volume1017
ISSN (Print)0272-9172

Conference

ConferenceLow-Dimensional Materials- Synthesis, Assembly, Property Scaling, and Modeling - 2007 MRS Spring Meeting
Country/TerritoryUnited States
CitySan Francisco, CA
Period9/04/0713/04/07

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