Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures

Minh Chien Nguyen; Ngoc Thanh Duong; Hong Woon Yun; Van Dam Do; Van Tu Vu; Whan Kyun Kim; Vu Khac Dat; Huamin Li; Woo Jong Yu

doi:10.1109/ESSERC66193.2025.11213978

Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures

Minh Chien Nguyen
, Ngoc Thanh Duong
, Hong Woon Yun
, Van Dam Do
, Van Tu Vu
, Whan Kyun Kim
, Vu Khac Dat
, Huamin Li
, Woo Jong Yu

Sungkyunkwan University
Samsung
SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

We present the first experimental demonstration and performance analysis of reconfigurable, ultra-fast nonvolatile floating gate memory (R-FGM) based on WSe₂/h- BN/graphene van der Waals (vdW) heterostructures. The device features an asymmetrically engineered WSe2 channel with top (TE) and bottom (BE) contacts, where the shielding effect of BE enables n-type and p-type memory reconfiguration through electric field control via Si/SiO₂ gate. Benefiting from ultra-clean vdW interfaces, the R-FGM achieves a program/erase speed of 30 ns, excellent data retention up to 10⁴s, and endurance over 10⁵ cycles while maintaining an on/off ratio exceeding 10⁶ for both memory types. Furthermore, the device exhibits multi-conductance states with 7 -bit operation, supporting long-term potentiation (LTP) and long-term depression (LTD) to emulate synaptic behavior. These results establish R-FGM as a promising candidate for next-generation non-volatile memory and neuromorphic computing applications.

Original language	English
Title of host publication	Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Publisher	IEEE Computer Society
Pages	245-248
Number of pages	4
ISBN (Electronic)	9798331525392
DOIs	https://doi.org/10.1109/ESSERC66193.2025.11213978
State	Published - 2025
Externally published	Yes
Event	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 - Munich, Germany Duration: 8 Sep 2025 → 11 Sep 2025

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Country/Territory	Germany
City	Munich
Period	8/09/25 → 11/09/25

Keywords

2D materials
floating-gate memory
neuromorphic computing
reconfigurable
ultrafast
van der Waals heterostructures

Access to Document

10.1109/ESSERC66193.2025.11213978

Cite this

Nguyen, M. C., Duong, N. T., Yun, H. W., Do, V. D., Vu, V. T., Kim, W. K., Dat, V. K., Li, H., & Yu, W. J. (2025). Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures. In Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 (pp. 245-248). (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSERC66193.2025.11213978

@inproceedings{72e61026097f41bebe1ba4c4940e5d54,

title = "Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures",

abstract = "We present the first experimental demonstration and performance analysis of reconfigurable, ultra-fast nonvolatile floating gate memory (R-FGM) based on WSe2/h- BN/graphene van der Waals (vdW) heterostructures. The device features an asymmetrically engineered WSe2 channel with top (TE) and bottom (BE) contacts, where the shielding effect of BE enables n-type and p-type memory reconfiguration through electric field control via Si/SiO2 gate. Benefiting from ultra-clean vdW interfaces, the R-FGM achieves a program/erase speed of 30 ns, excellent data retention up to 104s, and endurance over 105 cycles while maintaining an on/off ratio exceeding 106 for both memory types. Furthermore, the device exhibits multi-conductance states with 7 -bit operation, supporting long-term potentiation (LTP) and long-term depression (LTD) to emulate synaptic behavior. These results establish R-FGM as a promising candidate for next-generation non-volatile memory and neuromorphic computing applications.",

keywords = "2D materials, floating-gate memory, neuromorphic computing, reconfigurable, ultrafast, van der Waals heterostructures",

author = "Nguyen, \{Minh Chien\} and Duong, \{Ngoc Thanh\} and Yun, \{Hong Woon\} and Do, \{Van Dam\} and Vu, \{Van Tu\} and Kim, \{Whan Kyun\} and Dat, \{Vu Khac\} and Huamin Li and Yu, \{Woo Jong\}",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 ; Conference date: 08-09-2025 Through 11-09-2025",

year = "2025",

doi = "10.1109/ESSERC66193.2025.11213978",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "245--248",

booktitle = "Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025",

}

Nguyen, MC, Duong, NT, Yun, HW, Do, VD, Vu, VT, Kim, WK, Dat, VK, Li, H & Yu, WJ 2025, Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures. in Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. European Solid-State Circuits Conference, IEEE Computer Society, pp. 245-248, 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025, Munich, Germany, 8/09/25. https://doi.org/10.1109/ESSERC66193.2025.11213978

Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures. / Nguyen, Minh Chien; Duong, Ngoc Thanh; Yun, Hong Woon et al.
Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society, 2025. p. 245-248 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures

AU - Nguyen, Minh Chien

AU - Duong, Ngoc Thanh

AU - Yun, Hong Woon

AU - Do, Van Dam

AU - Vu, Van Tu

AU - Kim, Whan Kyun

AU - Dat, Vu Khac

AU - Li, Huamin

AU - Yu, Woo Jong

PY - 2025

Y1 - 2025

N2 - We present the first experimental demonstration and performance analysis of reconfigurable, ultra-fast nonvolatile floating gate memory (R-FGM) based on WSe2/h- BN/graphene van der Waals (vdW) heterostructures. The device features an asymmetrically engineered WSe2 channel with top (TE) and bottom (BE) contacts, where the shielding effect of BE enables n-type and p-type memory reconfiguration through electric field control via Si/SiO2 gate. Benefiting from ultra-clean vdW interfaces, the R-FGM achieves a program/erase speed of 30 ns, excellent data retention up to 104s, and endurance over 105 cycles while maintaining an on/off ratio exceeding 106 for both memory types. Furthermore, the device exhibits multi-conductance states with 7 -bit operation, supporting long-term potentiation (LTP) and long-term depression (LTD) to emulate synaptic behavior. These results establish R-FGM as a promising candidate for next-generation non-volatile memory and neuromorphic computing applications.

AB - We present the first experimental demonstration and performance analysis of reconfigurable, ultra-fast nonvolatile floating gate memory (R-FGM) based on WSe2/h- BN/graphene van der Waals (vdW) heterostructures. The device features an asymmetrically engineered WSe2 channel with top (TE) and bottom (BE) contacts, where the shielding effect of BE enables n-type and p-type memory reconfiguration through electric field control via Si/SiO2 gate. Benefiting from ultra-clean vdW interfaces, the R-FGM achieves a program/erase speed of 30 ns, excellent data retention up to 104s, and endurance over 105 cycles while maintaining an on/off ratio exceeding 106 for both memory types. Furthermore, the device exhibits multi-conductance states with 7 -bit operation, supporting long-term potentiation (LTP) and long-term depression (LTD) to emulate synaptic behavior. These results establish R-FGM as a promising candidate for next-generation non-volatile memory and neuromorphic computing applications.

KW - 2D materials

KW - floating-gate memory

KW - neuromorphic computing

KW - reconfigurable

KW - ultrafast

KW - van der Waals heterostructures

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U2 - 10.1109/ESSERC66193.2025.11213978

DO - 10.1109/ESSERC66193.2025.11213978

M3 - Conference contribution

AN - SCOPUS:105024532521

T3 - European Solid-State Circuits Conference

SP - 245

EP - 248

BT - Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025

PB - IEEE Computer Society

T2 - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025

Y2 - 8 September 2025 through 11 September 2025

ER -

Nguyen MC, Duong NT, Yun HW, Do VD, Vu VT, Kim WK et al. Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures. In Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society. 2025. p. 245-248. (European Solid-State Circuits Conference). doi: 10.1109/ESSERC66193.2025.11213978

Reconfigurable and Ultrafast Non-Volatile Floating-Gate Memory Based on van der Waals Heterostructures

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Keywords

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