Real-time skeletonization using FPGA

Thinning algorithms(or skeletonization) that extract feature parameters from an image are widely used in image processing. One of the most important issues in thinning is to reduce the execution time. Thus, many thinning algorithms have been proposed. But few attempts have been made to implement the thinning algorithms in real-time. The implementation of real-time skeletonization that has a large number of calculations is very difficult. This paper proposes hardware architecture that can output the thinned image to synchronize with the input image. The proposed architecture is implemented using the FPGA(Field Programable Gate Array) based vision system.