PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

This paper proposes PVT-invariant single-to-differential signal converter (SDC) applicable to the output circuitry of high-speed DDR SDRAM. The proposed SDC generates PVT-invariant differential-output sampling clock using a phase interpolation technique and a symmetric structure, and improves the aperture window of output data in source synchronous DDR SDRAM. The proposed SDC was simulated using 1.8-V 80-nm DRAM technology. The comparison result indicates that the differential clocks generated by the proposed SDC achieve 80.6% reduction of skew, 76.6% reduction of duty-cycle distortion, 61.7% of reduction of delay variation, and 8.5% reduction of maximum current for a given process, voltage, and temperature (PVT) variations, as compared to conventional SDCs. The I/O interface of a source-synchronous DDR SDRAM designed using the proposed SDC, which is operating at 1.0-Gbps/pin data rate has aperture window increased by 15.3% and ISI improved by 67.7% in comparison to conventional I/O interface.