Practical high-resolution programmable josephson voltage standards using double- and triple-stacked MoSi2-barrier junctions

Yonuk Chong; C. J. Burroughs; P. D. Dresselhaus; N. Hadacek; H. Yamamori; S. P. Benz

doi:10.1109/TASC.2005.849874

Practical high-resolution programmable josephson voltage standards using double- and triple-stacked MoSi₂-barrier junctions

Yonuk Chong
, C. J. Burroughs
, P. D. Dresselhaus
, N. Hadacek
, H. Yamamori
, S. P. Benz

Research output: Contribution to journal › Article › peer-review

46 Scopus citations

Abstract

We have developed vertically stacked supercon-ductor- normal-metal- superconductor Josephson junction technology for the next-generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double-and triple- stacked MoSi₂ barrier Josephson junctions with over 100 000 junctions operating simultaneously on a 1 cm × 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.

Original language	English
Pages (from-to)	461-464
Number of pages	4
Journal	IEEE Transactions on Applied Superconductivity
Volume	15
Issue number	2 PART I
DOIs	https://doi.org/10.1109/TASC.2005.849874
State	Published - Jun 2005
Externally published	Yes

Keywords

Josephson arrays
Programmable voltage standard
Superconducting integrated circuits
Superconductor-normal-superconductor devices

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10.1109/TASC.2005.849874

Cite this

@article{4bcd0fda2a504d418cb0242ac70842d5,

title = "Practical high-resolution programmable josephson voltage standards using double- and triple-stacked MoSi2-barrier junctions",

abstract = "We have developed vertically stacked supercon-ductor- normal-metal- superconductor Josephson junction technology for the next-generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double-and triple- stacked MoSi2 barrier Josephson junctions with over 100 000 junctions operating simultaneously on a 1 cm × 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.",

keywords = "Josephson arrays, Programmable voltage standard, Superconducting integrated circuits, Superconductor-normal-superconductor devices",

author = "Yonuk Chong and Burroughs, \{C. J.\} and Dresselhaus, \{P. D.\} and N. Hadacek and H. Yamamori and Benz, \{S. P.\}",

year = "2005",

month = jun,

doi = "10.1109/TASC.2005.849874",

language = "English",

volume = "15",

pages = "461--464",

journal = "IEEE Transactions on Applied Superconductivity",

issn = "1051-8223",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2 PART I",

}

TY - JOUR

T1 - Practical high-resolution programmable josephson voltage standards using double- and triple-stacked MoSi2-barrier junctions

AU - Chong, Yonuk

AU - Burroughs, C. J.

AU - Dresselhaus, P. D.

AU - Hadacek, N.

AU - Yamamori, H.

AU - Benz, S. P.

PY - 2005/6

Y1 - 2005/6

N2 - We have developed vertically stacked supercon-ductor- normal-metal- superconductor Josephson junction technology for the next-generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double-and triple- stacked MoSi2 barrier Josephson junctions with over 100 000 junctions operating simultaneously on a 1 cm × 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.

AB - We have developed vertically stacked supercon-ductor- normal-metal- superconductor Josephson junction technology for the next-generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double-and triple- stacked MoSi2 barrier Josephson junctions with over 100 000 junctions operating simultaneously on a 1 cm × 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.

KW - Josephson arrays

KW - Programmable voltage standard

KW - Superconducting integrated circuits

KW - Superconductor-normal-superconductor devices

UR - https://www.scopus.com/pages/publications/22044445693

U2 - 10.1109/TASC.2005.849874

DO - 10.1109/TASC.2005.849874

M3 - Article

AN - SCOPUS:22044445693

SN - 1051-8223

VL - 15

SP - 461

EP - 464

JO - IEEE Transactions on Applied Superconductivity

JF - IEEE Transactions on Applied Superconductivity

IS - 2 PART I

ER -

Practical high-resolution programmable josephson voltage standards using double- and triple-stacked MoSi₂-barrier junctions

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Keywords

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