Power-efficient fast write and hidden refresh of ReRAM using an ADC-based sense amplifier

Sang Yun Kim; Jong Min Baek; Dong Jin Seo; Jae Koo Park; Jung Hoon Chun; Kee Won Kwon

doi:10.1109/TCSII.2013.2281767

Power-efficient fast write and hidden refresh of ReRAM using an ADC-based sense amplifier

Sang Yun Kim, Jong Min Baek, Dong Jin Seo, Jae Koo Park, Jung Hoon Chun, Kee Won Kwon

Department of Semiconductor Systems Engineering

Sungkyunkwan University

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

An ADC-based current-mode sense amplifier and its usage to improve speed, power efficiency, and reliability of ReRAM are proposed. The adaptive step-size control of incremental step pulse programming enables 2.25 times faster write with 50% power. The degradation of ReRAM cells due to aging can be recovered by hidden refresh without sacrificing system performance. The test circuits are fabricated using a 350-nm technology and integrated with a 1-Kb HfO_x array chip.

Original language	English
Article number	6615953
Pages (from-to)	776-780
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	60
Issue number	11
DOIs	https://doi.org/10.1109/TCSII.2013.2281767
State	Published - 2013

Keywords

ADC
Fast write
Hidden refresh
Incremental step pulse programming (ISPP)
ReRAM
Sense amplifier (SA)

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10.1109/TCSII.2013.2281767

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title = "Power-efficient fast write and hidden refresh of ReRAM using an ADC-based sense amplifier",

abstract = "An ADC-based current-mode sense amplifier and its usage to improve speed, power efficiency, and reliability of ReRAM are proposed. The adaptive step-size control of incremental step pulse programming enables 2.25 times faster write with 50\% power. The degradation of ReRAM cells due to aging can be recovered by hidden refresh without sacrificing system performance. The test circuits are fabricated using a 350-nm technology and integrated with a 1-Kb HfOx array chip.",

keywords = "ADC, Fast write, Hidden refresh, Incremental step pulse programming (ISPP), ReRAM, Sense amplifier (SA)",

author = "Kim, \{Sang Yun\} and Baek, \{Jong Min\} and Seo, \{Dong Jin\} and Park, \{Jae Koo\} and Chun, \{Jung Hoon\} and Kwon, \{Kee Won\}",

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AU - Kim, Sang Yun

AU - Baek, Jong Min

AU - Seo, Dong Jin

AU - Park, Jae Koo

AU - Chun, Jung Hoon

AU - Kwon, Kee Won

PY - 2013

Y1 - 2013

N2 - An ADC-based current-mode sense amplifier and its usage to improve speed, power efficiency, and reliability of ReRAM are proposed. The adaptive step-size control of incremental step pulse programming enables 2.25 times faster write with 50% power. The degradation of ReRAM cells due to aging can be recovered by hidden refresh without sacrificing system performance. The test circuits are fabricated using a 350-nm technology and integrated with a 1-Kb HfOx array chip.

AB - An ADC-based current-mode sense amplifier and its usage to improve speed, power efficiency, and reliability of ReRAM are proposed. The adaptive step-size control of incremental step pulse programming enables 2.25 times faster write with 50% power. The degradation of ReRAM cells due to aging can be recovered by hidden refresh without sacrificing system performance. The test circuits are fabricated using a 350-nm technology and integrated with a 1-Kb HfOx array chip.

KW - ADC

KW - Fast write

KW - Hidden refresh

KW - Incremental step pulse programming (ISPP)

KW - ReRAM

KW - Sense amplifier (SA)

UR - https://www.scopus.com/pages/publications/84888387147

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JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 11

M1 - 6615953

ER -

Power-efficient fast write and hidden refresh of ReRAM using an ADC-based sense amplifier

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Keywords

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