Power-aware scheduling of conditional task graphs in real-time multiprocessor systems

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Abstract

We propose a novel power-aware task scheduling algorithm for DVS-enabled real-time multiprocessor systems. Unlike the existing algorithms, the proposed DVS algorithm can handle conditional task graphs (CTGs) which model more complex precedence constraints. We first propose a condition-unaware task scheduling algorithm integrating the task ordering algorithm for CTGs and the task stretching algorithm for unconditional task graphs. We then describe a condition-aware task scheduling algorithm which assigns to each task the start time and the clock speed, taking account of the condition matching and task execution profiles. Experimental results show that the proposed condition-aware task scheduling algorithm can reduce the energy consumption by 50% on average over the non-DVS task scheduling algorithm.

Original languageEnglish
Title of host publicationISLPED 2003 - Proceedings of the 2003 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages408-413
Number of pages6
ISBN (Electronic)158113682X
DOIs
StatePublished - 2003
Externally publishedYes
Event2003 International Symposium on Low Power Electronics and Design, ISLPED 2003 - Seoul, Korea, Republic of
Duration: 25 Aug 200327 Aug 2003

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2003-January
ISSN (Print)1533-4678

Conference

Conference2003 International Symposium on Low Power Electronics and Design, ISLPED 2003
Country/TerritoryKorea, Republic of
CitySeoul
Period25/08/0327/08/03

Keywords

  • Algorithm design and analysis
  • Clocks
  • Computer science
  • Dynamic voltage scaling
  • Energy consumption
  • Multiprocessing systems
  • Power engineering and energy
  • Real time systems
  • Scheduling algorithm
  • Voltage control

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