Abstract
We propose a novel power-aware task scheduling algorithm for DVS-enabled real-time multiprocessor systems. Unlike the existing algorithms, the proposed DVS algorithm can handle conditional task graphs (CTGs) which model more complex precedence constraints. We first propose a condition-unaware task scheduling algorithm integrating the task ordering algorithm for CTGs and the task stretching algorithm for unconditional task graphs. We then describe a condition-aware task scheduling algorithm which assigns to each task the start time and the clock speed, taking account of the condition matching and task execution profiles. Experimental results show that the proposed condition-aware task scheduling algorithm can reduce the energy consumption by 50% on average over the non-DVS task scheduling algorithm.
| Original language | English |
|---|---|
| Pages (from-to) | 408-413 |
| Number of pages | 6 |
| Journal | Proceedings of the International Symposium on Low Power Electronics and Design |
| DOIs | |
| State | Published - 2003 |
| Externally published | Yes |
| Event | Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) - Seoul, Korea, Republic of Duration: 25 Aug 2003 → 27 Aug 2003 |
Keywords
- Conditional task graph
- Dynamic voltage scaling
- Multiprocessor
- Real-time systems
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