Pipelined hardware architecture for high-speed optical flow estimation using FPGA

Seunghun Jin; Dongkyun Kim; Dung Duc Nguyen; Jae Wook Jeon

doi:10.1109/FCCM.2010.14

Pipelined hardware architecture for high-speed optical flow estimation using FPGA

Seunghun Jin
, Dongkyun Kim
, Dung Duc Nguyen
, Jae Wook Jeon

Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Optical flow is a motion field estimation method that has a wide range of applications. In this paper, we present a fully pipelined hardware architecture for high-speed optical flow estimation based on a full-search block matching algorithm. A census transform is applied to the corresponding pixels in the current and previous frame. The similarity between two census vectors within the search area is then computed by measuring the hamming distance. Macro blocks are generated based on the measured hamming distance values and the best match is determined by locating the block that has the smallest sum. The synthesis tool reported that the proposed system is capable of processing 400 standard VGA frames per second.

Original language	English
Title of host publication	Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010
Pages	33-36
Number of pages	4
DOIs	https://doi.org/10.1109/FCCM.2010.14
State	Published - 2010
Externally published	Yes
Event	18th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010 - Charlotte, NC, United States Duration: 2 May 2010 → 4 May 2010

Publication series

Name	Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010

Conference

Conference	18th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010
Country/Territory	United States
City	Charlotte, NC
Period	2/05/10 → 4/05/10

Keywords

FPGA
Hardware architecture
Optical flow
VHDL

Access to Document

10.1109/FCCM.2010.14

Cite this

Jin, S., Kim, D., Nguyen, D. D., & Jeon, J. W. (2010). Pipelined hardware architecture for high-speed optical flow estimation using FPGA. In Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010 (pp. 33-36). Article 5474074 (Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010). https://doi.org/10.1109/FCCM.2010.14

@inproceedings{761581ff003b45279dbd558cecb4edb6,

title = "Pipelined hardware architecture for high-speed optical flow estimation using FPGA",

abstract = "Optical flow is a motion field estimation method that has a wide range of applications. In this paper, we present a fully pipelined hardware architecture for high-speed optical flow estimation based on a full-search block matching algorithm. A census transform is applied to the corresponding pixels in the current and previous frame. The similarity between two census vectors within the search area is then computed by measuring the hamming distance. Macro blocks are generated based on the measured hamming distance values and the best match is determined by locating the block that has the smallest sum. The synthesis tool reported that the proposed system is capable of processing 400 standard VGA frames per second.",

keywords = "FPGA, Hardware architecture, Optical flow, VHDL",

author = "Seunghun Jin and Dongkyun Kim and Nguyen, \{Dung Duc\} and Jeon, \{Jae Wook\}",

year = "2010",

doi = "10.1109/FCCM.2010.14",

language = "English",

isbn = "9780769540566",

series = "Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010",

pages = "33--36",

booktitle = "Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010",

note = "18th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010 ; Conference date: 02-05-2010 Through 04-05-2010",

}

Jin, S, Kim, D, Nguyen, DD & Jeon, JW 2010, Pipelined hardware architecture for high-speed optical flow estimation using FPGA. in Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010., 5474074, Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, pp. 33-36, 18th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, NC, United States, 2/05/10. https://doi.org/10.1109/FCCM.2010.14

Pipelined hardware architecture for high-speed optical flow estimation using FPGA. / Jin, Seunghun; Kim, Dongkyun; Nguyen, Dung Duc et al.
Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010. 2010. p. 33-36 5474074 (Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Pipelined hardware architecture for high-speed optical flow estimation using FPGA

AU - Jin, Seunghun

AU - Kim, Dongkyun

AU - Nguyen, Dung Duc

AU - Jeon, Jae Wook

PY - 2010

Y1 - 2010

N2 - Optical flow is a motion field estimation method that has a wide range of applications. In this paper, we present a fully pipelined hardware architecture for high-speed optical flow estimation based on a full-search block matching algorithm. A census transform is applied to the corresponding pixels in the current and previous frame. The similarity between two census vectors within the search area is then computed by measuring the hamming distance. Macro blocks are generated based on the measured hamming distance values and the best match is determined by locating the block that has the smallest sum. The synthesis tool reported that the proposed system is capable of processing 400 standard VGA frames per second.

AB - Optical flow is a motion field estimation method that has a wide range of applications. In this paper, we present a fully pipelined hardware architecture for high-speed optical flow estimation based on a full-search block matching algorithm. A census transform is applied to the corresponding pixels in the current and previous frame. The similarity between two census vectors within the search area is then computed by measuring the hamming distance. Macro blocks are generated based on the measured hamming distance values and the best match is determined by locating the block that has the smallest sum. The synthesis tool reported that the proposed system is capable of processing 400 standard VGA frames per second.

KW - FPGA

KW - Hardware architecture

KW - Optical flow

KW - VHDL

UR - https://www.scopus.com/pages/publications/77954276877

U2 - 10.1109/FCCM.2010.14

DO - 10.1109/FCCM.2010.14

M3 - Conference contribution

AN - SCOPUS:77954276877

SN - 9780769540566

T3 - Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010

SP - 33

EP - 36

BT - Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010

T2 - 18th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010

Y2 - 2 May 2010 through 4 May 2010

ER -

Pipelined hardware architecture for high-speed optical flow estimation using FPGA

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Keywords

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