TY - GEN
T1 - Persistent Memory I/O-Aware Task Placement for Mitigating Resource Contention
AU - Ahn, Hyunwoo
AU - Kim, Jongseok
AU - Seo, Euiseong
N1 - Publisher Copyright:
© 2024 ACM.
PY - 2024/9/4
Y1 - 2024/9/4
N2 - Direct access (DAX) file systems for persistent memory (PM) perform reads and writes through load and store instructions, respectively, bypassing the I/O path inside the operating system (OS) kernel. However, because of this, the OS is unable to differentiate PM I/O tasks from CPU-bound tasks, resulting in them being treated equally in task placement. PM I/O-oblivious task placement significantly impacts the DRAM access performance of co-located tasks due to severe resource contention on the memory controller, particularly with remote PM access. Moreover, such task placement fails to utilize on-chip idle resources from the stall cycles for PM I/O, impacting the efficacy of simultaneous multi-threading (SMT). We propose a PM I/O-aware task placement scheme that detects PM I/O activities and dynamically places tasks to mitigate the memory controller contention and to efficiently utilize the idle on-chip resources. In our evaluation, PM I/O-oblivious task placement caused FIO to run over five times slower and reduced SPEC CPU performance by more than three times compared to optimal placements. However, our proposed approach limited the average performance loss to just 3.3% across both workloads, with a maximum loss of only 4.9%.
AB - Direct access (DAX) file systems for persistent memory (PM) perform reads and writes through load and store instructions, respectively, bypassing the I/O path inside the operating system (OS) kernel. However, because of this, the OS is unable to differentiate PM I/O tasks from CPU-bound tasks, resulting in them being treated equally in task placement. PM I/O-oblivious task placement significantly impacts the DRAM access performance of co-located tasks due to severe resource contention on the memory controller, particularly with remote PM access. Moreover, such task placement fails to utilize on-chip idle resources from the stall cycles for PM I/O, impacting the efficacy of simultaneous multi-threading (SMT). We propose a PM I/O-aware task placement scheme that detects PM I/O activities and dynamically places tasks to mitigate the memory controller contention and to efficiently utilize the idle on-chip resources. In our evaluation, PM I/O-oblivious task placement caused FIO to run over five times slower and reduced SPEC CPU performance by more than three times compared to optimal placements. However, our proposed approach limited the average performance loss to just 3.3% across both workloads, with a maximum loss of only 4.9%.
KW - Direct Access File Systems
KW - Load Balancing
KW - Operating Systems
KW - Persistent Memory
KW - Scheduling
UR - https://www.scopus.com/pages/publications/85205127013
U2 - 10.1145/3678015.3680482
DO - 10.1145/3678015.3680482
M3 - Conference contribution
AN - SCOPUS:85205127013
T3 - APSys 2024 - Proceedings of the 15th ACM SIGOPS Asia-Pacific Workshop on Systems
SP - 8
EP - 14
BT - APSys 2024 - Proceedings of the 15th ACM SIGOPS Asia-Pacific Workshop on Systems
PB - Association for Computing Machinery, Inc
T2 - 15th ACM SIGOPS Asia-Pacific Workshop on Systems, APSys 2024
Y2 - 4 September 2024 through 5 September 2024
ER -