Performance benchmarks for Si, III-V, TFET, and carbon nanotube FET - Re-thinking the technology assessment methodology for complementary logic applications

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Aspiring emerging device technologies (e.g. III-V, CNFET, TFET) are often targeted to outperform Si FETs at the same off-state current (Ioff) and supply voltage (Vdd). We present a new device technology assessment methodology based on energy-delay optimization which treats I off and Vdd as "free variables", and bounded by constraints due to device variation and circuit noise margin. We show that for each emerging device (III-V, CNFET, TFET), there is a corresponding and different optimal set of Ioff and Vdd, and an optimal energy-delay. Today's best-available III-V and CNFET can outperform the best Si FET by 1.5-2x and 2-3.5x, respectively. Projected into the 10nm gate length regime, III-V-on-Insulator, CNFET, and TFET are 1.25x, 2-3x, and 5-10x (for FO1 delays of 0.3ns, 0.1ns, and 1ns respectively) better than the ITRS target at the same gate length.

Original languageEnglish
Title of host publication2010 IEEE International Electron Devices Meeting, IEDM 2010
Pages16.2.1-16.2.4
DOIs
StatePublished - 2010
Externally publishedYes
Event2010 IEEE International Electron Devices Meeting, IEDM 2010 - San Francisco, CA, United States
Duration: 6 Dec 20108 Dec 2010

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2010 IEEE International Electron Devices Meeting, IEDM 2010
Country/TerritoryUnited States
CitySan Francisco, CA
Period6/12/108/12/10

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