Parasitic Capacitance Prediction for Standard Cells Using Machine Learning and K-Means Clustering Algorithm

With the continuous scaling of process nodes in the semiconductor industry, the importance of accurately predicting parasitic capacitance based on layout characteristics has increased significantly. This is especially important because post-layout parasitic capacitance can have a significant impact on power consumption and overall circuit performance. However, conventional method for parasitic capacitance extraction is time-consuming as it must be iterated from layout to post-layout extraction and simulation. This is one of the critical factors of delay in the chip design flow. In this study, we propose a method to predict parasitic capacitance for standard cells using an artificial neural network (ANN) model. The standard cells for training the ANN model were generated using a 3 nm process and buried power rail (BPR) was applied for backside power delivery network (BSPDN). The ANN model using netlist parameters can predict parasitic capacitance with over 98% accuracy compared to StarRC. Then, K-means clustering is applied to minimize data sampling. The K-means clustering algorithm was employed to reduce the dataset size by 68.25% for model training. The ANN model trained on the sampled data showed 98% accuracy. The ANN model using training data sampled by K-means clustering is an efficient alternative for accurate and fast parasitic capacitance extraction.