Optimization of double gate vertical channel tunneling field effect transistor (DVTFET) with dielectric sidewall

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage (V_amb) and double gate structure is applied to improve on-current (I_ON) and subthreshold swing (SS). We discussed the fin width (W_S), body doping concentration, sidewall width (W_side), drain and gate underlap distance (X_d), source doping distance (X_S) and pocket doping length (X_P) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high I_ON of 1.2 × 10^-3 A/μm m and low V_amb of -2.0 V.