TY - GEN
T1 - Optimal shape of retainer ring considering edge exclusion and slurry film thickness
AU - Park, Jinwoo
AU - Shin, Cheolmin
AU - Kim, Taesung
AU - Qin, Hongyi
N1 - Publisher Copyright:
© 2015 American Vacuum Society.
PY - 2016/2/17
Y1 - 2016/2/17
N2 - Microelectronic devices continue to decrease in size, current features reached to 14 nm ARM processor, such as Exynos 7 octa in Samsung electronics. The semiconductor industry requires a deeper understanding of the physical processes involved in CMP to help attain smoother surfaces. In the CMP process, yield efficiency decreases by generating edge exclusion. And slurry cost may contribute to almost half of the total cost of ownership. In this situation, retainer ring can regulate edge exclusion and slurry flow rate. For manufacturing optimal shape of retainer ring, we consider edge exclusion and slurry film thickness. In this study, we focus on the former. In order to research edge exclusion, we perform numerical analysis using ANSYS mechanical which analyzes stress distribution on the wafer. And, after manufacturing prototype, we investigate friction force, temperature and removal rate of wafer in 300 mm wafer scale condition experiment.
AB - Microelectronic devices continue to decrease in size, current features reached to 14 nm ARM processor, such as Exynos 7 octa in Samsung electronics. The semiconductor industry requires a deeper understanding of the physical processes involved in CMP to help attain smoother surfaces. In the CMP process, yield efficiency decreases by generating edge exclusion. And slurry cost may contribute to almost half of the total cost of ownership. In this situation, retainer ring can regulate edge exclusion and slurry flow rate. For manufacturing optimal shape of retainer ring, we consider edge exclusion and slurry film thickness. In this study, we focus on the former. In order to research edge exclusion, we perform numerical analysis using ANSYS mechanical which analyzes stress distribution on the wafer. And, after manufacturing prototype, we investigate friction force, temperature and removal rate of wafer in 300 mm wafer scale condition experiment.
UR - https://www.scopus.com/pages/publications/84964522998
M3 - Conference contribution
AN - SCOPUS:84964522998
T3 - 2015 International Conference on Planarization/CMP Technology, ICPT 2015
BT - 2015 International Conference on Planarization/CMP Technology, ICPT 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International Conference on Planarization/CMP Technology, ICPT 2015
Y2 - 30 September 2015 through 2 October 2015
ER -