Open-loop per-pin skew compensation with lock fault detector for parallel NAND flash memory interface

An open-loop per-pin skew compensation with lock fault detection is presented. The proposed circuit employs an open-loop reference selector, a two-stage open-loop delay lock method which is separated by a coarse and fine lock for fast lock-in time, and a fault lock detecting scheme to prevent lock fault by dead zone of samplers. A unidirectional scan method ahead the fine lock stage to minimise pinto-pin skew errors after calibration is also applied. The circuit was fabricated with 55 nm CMOS technology with a 1 V supply voltage and an area of 0.0036 mm2 for one de-skewing module. The measured result shows that the skew error at 1 GHz operation was reduced to <6 ps after skew calibration when the skew between input/output (IO) pins was 230 ps, and the lock-in time was 11 clock cycles.