TY - GEN
T1 - On-chip layout optimization of synchronous DC-DC buck converter for EMI reduction
AU - Joo, Soyeon
AU - Hwang, Jisoo
AU - Song, Eunseok
AU - Kim, So Young
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/2
Y1 - 2017/7/2
N2 - In this work, we analyzed the noise occurring at the switching node of a synchronous DC-DC converter in on-chip level according to the metal layers and optimized the layout to reduce that noise. By sweeping the metal width and changing the arrangement of the pass transistor, the peak voltage level and the maximum of the near field were estimated through HFSS simulation. As a result, alternately arranging the PMOS and NMOS pass transistor shows lower peak voltage level. Moreover, there is an optimum metal width to reduce near field occurring at the switching node.
AB - In this work, we analyzed the noise occurring at the switching node of a synchronous DC-DC converter in on-chip level according to the metal layers and optimized the layout to reduce that noise. By sweeping the metal width and changing the arrangement of the pass transistor, the peak voltage level and the maximum of the near field were estimated through HFSS simulation. As a result, alternately arranging the PMOS and NMOS pass transistor shows lower peak voltage level. Moreover, there is an optimum metal width to reduce near field occurring at the switching node.
KW - EMI (Electromagnetic Interference)
KW - Synchronous DC-DC buck converter
UR - https://www.scopus.com/pages/publications/85050494077
U2 - 10.1109/EDAPS.2017.8277036
DO - 10.1109/EDAPS.2017.8277036
M3 - Conference contribution
AN - SCOPUS:85050494077
T3 - 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017
SP - 1
EP - 3
BT - 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017
Y2 - 14 December 2017 through 16 December 2017
ER -