Novel STI Technology for Enhancing Reliability of High-k/Metal Gate DRAM

The challenges associated with semiconductor are increasing because of the rapid changes in the semiconductor market and the extreme scaling of semiconductors, with some processes reaching their technological limits. In the case of gate dielectrics, these limitations can be overcome by adopting high-k metal gate (HKMG) architecture instead of the previously used poly silicon/silicon oxy-nitride (PSION) structure. However, implementing the HKMG in a conventional DRAM process degrades the gate oxide. Therefore, in this study, a shallow trench isolation (STI) technology was developed to improve the gate oxide reliability in gate first HKMG DRAM structures. A novel STI process was developed to prevent the reduction in the oxide growth that occurs when the STI seam (or void) generated during the STI gap fill process meets the low temperature gate oxide process of the HKMG with SiGe. With the spacer STI (S-STI) structure, the ALD spacer was formed in the STI space region before the STI gap fill process to control the position of the STI seam (or void). Thus, a favorable environment for the growth of the gate oxide was established under the reduced effect of STI seam, and the oxide reliability was improved while maintaining the original structure and processes of the HKMG DRAM. Various analyses confirmed that the reliability was enhanced without the inherent characteristics of the HKMG being affected. These results revealed that the STI integration technology introduced herein improves the oxide reliability of HKMG DRAM products and maintains their technological excellence for the various complex needs of a rapidly changing market.