Noise immunity modeling and analysis of delay-locked loop

Inyoung Park; Ikchan Jang; Wonjoo Jung; Soyoung Kim

doi:10.1109/SaPIW.2015.7237401

Noise immunity modeling and analysis of delay-locked loop

Inyoung Park
, Ikchan Jang
, Wonjoo Jung
, Soyoung Kim

Department of Semiconductor Systems Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Delay-locked loops (DLLs) have emerged an attractive alternative to the traditional phase-locked loops (PLLs). It is essential to understand and analyze the electromagnetic susceptibility of DLLs to ensure the proper operation of the system. In order to ascertain how the performance of DLL is affected by the external noise, we design a DLL using self-biased techniques and establish the noise immunity experiment with bulk current injection (BCI) method. We also construct the equivalent circuit model for circuit simulation and demonstrate its validity by comparing with the measurement results. Consequently, the RF noise immunity characteristics of the DLL varies with its frequency and magnitude. Particularly, we detect that the DLL circuit that we designed is very sensitive to the external noise with frequency around 75 MHz.

Original language	English
Title of host publication	SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467365819
DOIs	https://doi.org/10.1109/SaPIW.2015.7237401
State	Published - 2 Sep 2015
Event	19th IEEE Workshop on Signal and Power Integrity, SPI 2015 - Berlin, Germany Duration: 10 May 2015 → 13 May 2015

Publication series

Name	SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity

Conference

Conference	19th IEEE Workshop on Signal and Power Integrity, SPI 2015
Country/Territory	Germany
City	Berlin
Period	10/05/15 → 13/05/15

Keywords

Circuit simulation
delay-locked loop (DLL)
Electromagnetic compatibility
noise immunity

Access to Document

10.1109/SaPIW.2015.7237401

Cite this

@inproceedings{4208639374124365be7b9a0b32a64693,

title = "Noise immunity modeling and analysis of delay-locked loop",

abstract = "Delay-locked loops (DLLs) have emerged an attractive alternative to the traditional phase-locked loops (PLLs). It is essential to understand and analyze the electromagnetic susceptibility of DLLs to ensure the proper operation of the system. In order to ascertain how the performance of DLL is affected by the external noise, we design a DLL using self-biased techniques and establish the noise immunity experiment with bulk current injection (BCI) method. We also construct the equivalent circuit model for circuit simulation and demonstrate its validity by comparing with the measurement results. Consequently, the RF noise immunity characteristics of the DLL varies with its frequency and magnitude. Particularly, we detect that the DLL circuit that we designed is very sensitive to the external noise with frequency around 75 MHz.",

keywords = "Circuit simulation, delay-locked loop (DLL), Electromagnetic compatibility, noise immunity",

author = "Inyoung Park and Ikchan Jang and Wonjoo Jung and Soyoung Kim",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 19th IEEE Workshop on Signal and Power Integrity, SPI 2015 ; Conference date: 10-05-2015 Through 13-05-2015",

year = "2015",

month = sep,

day = "2",

doi = "10.1109/SaPIW.2015.7237401",

language = "English",

series = "SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity",

}

Park, I, Jang, I, Jung, W & Kim, S 2015, Noise immunity modeling and analysis of delay-locked loop. in SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity., 7237401, SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity, Institute of Electrical and Electronics Engineers Inc., 19th IEEE Workshop on Signal and Power Integrity, SPI 2015, Berlin, Germany, 10/05/15. https://doi.org/10.1109/SaPIW.2015.7237401

Noise immunity modeling and analysis of delay-locked loop. / Park, Inyoung; Jang, Ikchan; Jung, Wonjoo et al.
SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity. Institute of Electrical and Electronics Engineers Inc., 2015. 7237401 (SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Noise immunity modeling and analysis of delay-locked loop

AU - Park, Inyoung

AU - Jang, Ikchan

AU - Jung, Wonjoo

AU - Kim, Soyoung

PY - 2015/9/2

Y1 - 2015/9/2

N2 - Delay-locked loops (DLLs) have emerged an attractive alternative to the traditional phase-locked loops (PLLs). It is essential to understand and analyze the electromagnetic susceptibility of DLLs to ensure the proper operation of the system. In order to ascertain how the performance of DLL is affected by the external noise, we design a DLL using self-biased techniques and establish the noise immunity experiment with bulk current injection (BCI) method. We also construct the equivalent circuit model for circuit simulation and demonstrate its validity by comparing with the measurement results. Consequently, the RF noise immunity characteristics of the DLL varies with its frequency and magnitude. Particularly, we detect that the DLL circuit that we designed is very sensitive to the external noise with frequency around 75 MHz.

AB - Delay-locked loops (DLLs) have emerged an attractive alternative to the traditional phase-locked loops (PLLs). It is essential to understand and analyze the electromagnetic susceptibility of DLLs to ensure the proper operation of the system. In order to ascertain how the performance of DLL is affected by the external noise, we design a DLL using self-biased techniques and establish the noise immunity experiment with bulk current injection (BCI) method. We also construct the equivalent circuit model for circuit simulation and demonstrate its validity by comparing with the measurement results. Consequently, the RF noise immunity characteristics of the DLL varies with its frequency and magnitude. Particularly, we detect that the DLL circuit that we designed is very sensitive to the external noise with frequency around 75 MHz.

KW - Circuit simulation

KW - delay-locked loop (DLL)

KW - Electromagnetic compatibility

KW - noise immunity

UR - https://www.scopus.com/pages/publications/84957895217

U2 - 10.1109/SaPIW.2015.7237401

DO - 10.1109/SaPIW.2015.7237401

M3 - Conference contribution

AN - SCOPUS:84957895217

T3 - SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity

BT - SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 19th IEEE Workshop on Signal and Power Integrity, SPI 2015

Y2 - 10 May 2015 through 13 May 2015

ER -

Noise immunity modeling and analysis of delay-locked loop

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Keywords

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