New developments in Schottky source/drain high-k/metal gate CMOS transistors

Recent developments in Schottky source/drain high-k/metal gate CMOS transistors (SSDT) will be presented. Bulk SSDTs with 1.5-2 nm HfO₂ (or HfAlO) gate dielectric and HfN/TaN metal gate have been fabricated using a novel low temperature process. The Si N-SSDT using YbSi_2-x suicide, due to the lower Schottky electron barrier of YbSi_2.x/Si, has demonstrated a record high I_on/I_off ratio of ∼10 ⁷ and a steep subthreshold slope of 75 mV/dec. For P-SSDT, the Si SSDT using PtSi silicide S/D shows excellent I_on/I_off of ∼ 10⁷-10⁸ and subthreshold slope of ∼ 66 mV/dec, while the Ge SSDT using NiGe S/D shows I_on ∼ 5 times larger than that of the Si counterpart with PtSi S/D, due to the lower hole Schottky barrier and the higher hole mobility of Ge channel. The implant-free low temperature process relaxes the thermal budget of high-k dielectric and metal gate Fermi pinning. More improved performances are expected by using ultra-thin-body (UTB) SOI or GOI structures, showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.