Multi-Core Gateway Architecture and Scheduling Algorithm for High-Performance Gateway Implementation

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

As the functions of vehicles continue to diversify, the performances of the corresponding electronic control units (ECUs) are being significantly improved. Moreover, the communication speed and data size are also increasing. This can lead to a burden on the gateway, thereby causing problems to the gateway. Therefore, as the number of ECUs and communication performance increase, the performance of the gateway must also increase. In this paper, we propose a multi-core gateway, an operational algorithm, and a new scheduling algorithm for efficient data transfer. In addition, we confirmed that the proposed algorithm could address the problems in existing algorithms (FIFO, SP, and EDF) through comparison.

Original languageEnglish
Title of host publication2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728161648
DOIs
StatePublished - 1 Nov 2020
Externally publishedYes
Event2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020 - Seoul, Korea, Republic of
Duration: 1 Nov 20203 Nov 2020

Publication series

Name2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020

Conference

Conference2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020
Country/TerritoryKorea, Republic of
CitySeoul
Period1/11/203/11/20

Keywords

  • Gateway
  • Multi-core
  • Scheduling
  • Scheduling algorithm

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