Modified CeO₂ deposition process for high-k oxide gate dielectrics

In this paper, we report an investigation into the feasibility of using CeO₂ thin films as high-k oxide gate dielectrics. During the film growth using the r.f. reactive magnetron sputtering method, the insulator/silicon structure generates a SiO₂ layer at the interface. Therefore, prior to the insulator layer deposition, we placed an extremely thin metal layer as a seed layer that promoted insulator thin film deposition and prevented interfacial SiO₂ layer formation. By applying a Ce metal seed layer of about 4 nm, we were able to successfully suppress unwanted SiO₂ layer generation at the interface between the CeO₂ layer and the Si substrate. After a modified CeO₂ deposition process, dielectric constant was improved from 5.7 to 15. We also successfully achieved an interface trap density of CeO₂/Si as low as 8.76 × 10 ¹⁰ cm^-2eV^-1.