TY - GEN
T1 - Modeling of flip-chip interconnects using novel neural network approaches
AU - Hwangbo, Hoon
AU - Lee, Jaehoon
AU - Nah, Wansoo
AU - Joo, Jinho
AU - Jung, Seung Boo
PY - 2005
Y1 - 2005
N2 - In this paper, we present an efficient neural network approach to analyze the bump structure of flip-chip transitions. 3D FEM simulations are used to extract the network parameters such as s-parameters and then the equivalent lumped circuit model is used to extract L-C and R. Validation of the equivalent circuit model is conducted by the comparison between the circuit simulation and the full wave simulation. Using the extracted data, training sets of the neural networks are composed. The proposed neural network, in which all L-C and R parameters are used simultaneously at the one output layer, shows nice prediction performance for the s-parameter characteristics.
AB - In this paper, we present an efficient neural network approach to analyze the bump structure of flip-chip transitions. 3D FEM simulations are used to extract the network parameters such as s-parameters and then the equivalent lumped circuit model is used to extract L-C and R. Validation of the equivalent circuit model is conducted by the comparison between the circuit simulation and the full wave simulation. Using the extracted data, training sets of the neural networks are composed. The proposed neural network, in which all L-C and R parameters are used simultaneously at the one output layer, shows nice prediction performance for the s-parameter characteristics.
UR - https://www.scopus.com/pages/publications/33847190308
U2 - 10.1109/APMC.2005.1606521
DO - 10.1109/APMC.2005.1606521
M3 - Conference contribution
AN - SCOPUS:33847190308
SN - 078039433X
SN - 9780780394339
T3 - Asia-Pacific Microwave Conference Proceedings, APMC
BT - APMC 2005
T2 - APMC 2005: Asia-Pacific Microwave Conference 2005
Y2 - 4 December 2005 through 7 December 2005
ER -