Modeling and co-simulation of I/O interconnects for on-chip and off-chip EMI prediction

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

In this paper, modeling and co-simulation methodology is proposed to predict EMI noise from the switching activity of on-chip interconnects. The proposed model includes the model for I/O driver and the on-chip interconnect load, the PKG and the test PCB, and the conducted and radiated EMI simulation. Using the simulation results of the proposed model, the I/O driver and the interconnect design can be optimized for minimum chip level EMI noise.

Original languageEnglish
Title of host publication2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings
Pages821-824
Number of pages4
DOIs
StatePublished - 2012
Event2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Singapore, Singapore
Duration: 21 May 201224 May 2012

Publication series

Namecccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings

Conference

Conference2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012
Country/TerritorySingapore
CitySingapore
Period21/05/1224/05/12

Keywords

  • EMI
  • I/O driver
  • ICs
  • Interconnect
  • Switching current

Fingerprint

Dive into the research topics of 'Modeling and co-simulation of I/O interconnects for on-chip and off-chip EMI prediction'. Together they form a unique fingerprint.

Cite this