Memory die clustering and matching for optimal voltage window in semiconductor

In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being matched with a verification wafer. The proposed method makes the ability to apply a different voltage trimming condition for each dies internal voltage circuit depending on their characteristics, thereby improving the characteristics of the individual dies and reducing the fail bit count (FBC) further. The experimental results on the real-application case show that our proposed method reduces the FBC by 1%-5%, which contributes yield enhancement and quality improvement of DRAM memory by raising the efficiency of the redundancy cell repair in the repair process.