Abstract
This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.
| Original language | English |
|---|---|
| Pages (from-to) | 745-753 |
| Number of pages | 9 |
| Journal | Journal of Semiconductor Technology and Science |
| Volume | 16 |
| Issue number | 6 |
| DOIs | |
| State | Published - Dec 2016 |
Keywords
- Data bus
- Interconnect
- IoT
- Low power
- Wireless sensor node