Low-voltage CMOS differential logic style with supply voltage approaching device threshold

This brief describes a novel low-voltage CMOS differential logic operating with supply voltage approaching the MOS threshold voltage. The proposed logic style improves switching speed by boosting the gate-source voltage of transistors along timing-critical signal paths. The logic style also minimizes area overhead by allowing a single boosting circuit to be shared by complementary outputs. Test sets of logic gates were designed in a 0.18-μm CMOS process, whose comparison results indicated that the energy-delay product of the proposed logic style was improved by up to 86% compared with conventional logic styles at supply voltage ranging from 0.4 to 1.2 V. The experimental result for a 64-bit adder designed using the proposed logic style revealed an addition time of 4.8 ns at 0.5-V supply with 31 pJ at 100 MHz.