Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode

Both P- and N-channel MOSFETs with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420°C. PMOSFETs with PtSi S/D show excellent electrical performance of an I_on/I_off ∼ 10 ⁷-10⁸ and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi_2-x S/D have ∼3 orders of magnitude larger I _off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I_on/I_off ∼ 10⁵ at low drain voltage. It can be attributed to the relatively higher barrier height (Φ_n) of DySi_2-x/n-Si than that of PtSi/p-Si (Φ_p) and the rougher DySi_2-x film. Adding a thin intermediate Ge layer (∼1 nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed.