Low Power, Quick Settling time DLDO Architecture with Dynamic PID gain controller and Event Detector

This paper proposes a digital LDO circuit design through Dynamic gain PID digital feedback control and Event-Driven for low power and high-speed stability for controlling voltage. The advantage of building an Asynchronous Event-Driven DLDO design IP can reduce power loss due to efficient clock generation due to changes in Self-Triggering and Load Current compared to other DLDOs. Second, our structure maintains an accurate output voltage while showing good efficiency for latency through a PID controller. In addition, we use Event driven method to reduce the ripple of the output power voltage and clock power. We also use the parameter value of PID as an input parameter without fixing it. The Dynamic gain PID's input parameter values are input as a parameter from the Fuzzy logic algorithm. As a result, the setting time is faster than the general fixed PID controller. The DLDO architecture consists of a Dynamic PID controller with Fuzzy algorithm, PMOS array, and ADC.