TY - GEN
T1 - Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE application
AU - Lee, Dongsoo
AU - Kim, Sung Jin
AU - Oh, Seong Jin
AU - Won, Gyusub
AU - Nga Truong, Thi Kim
AU - Ali, Imran
AU - Abbasizadeh, Hamed
AU - Rikan, Behnam Samadpoor
AU - Lee, Kang Yoon
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/2/20
Y1 - 2018/2/20
N2 - This paper presents a low power FSK transceiver with ADPLL based on direct modulation and integrated SPDT switch for Bluetooth low energy application. To ensure that the proposed low power transceiver can operate at 1 Mbps data rate, FSK modulation is implemented using an ADPLL with direct modulation technique. The SPDT switch is integrated to share the antenna and matching network between the transmitter and receiver, thus minimizing the system cost by reducing external components. The transceiver is implemented using 1P6M 55-nm CMOS technology. The die area of the transceiver with DC-DC converter is 1.79 mm2. The power consumption of the Tx and Rx are 6 and 5 mW, respectively. The noise figure of Rx is up to 6.8 dB with respect to channel frequencies. The phase noise of the ADPLL is -84.7 and -118.9 dBc/Hz at 100 kHz and 1 MHz offset from 2.44 GHz, respectively.
AB - This paper presents a low power FSK transceiver with ADPLL based on direct modulation and integrated SPDT switch for Bluetooth low energy application. To ensure that the proposed low power transceiver can operate at 1 Mbps data rate, FSK modulation is implemented using an ADPLL with direct modulation technique. The SPDT switch is integrated to share the antenna and matching network between the transmitter and receiver, thus minimizing the system cost by reducing external components. The transceiver is implemented using 1P6M 55-nm CMOS technology. The die area of the transceiver with DC-DC converter is 1.79 mm2. The power consumption of the Tx and Rx are 6 and 5 mW, respectively. The noise figure of Rx is up to 6.8 dB with respect to channel frequencies. The phase noise of the ADPLL is -84.7 and -118.9 dBc/Hz at 100 kHz and 1 MHz offset from 2.44 GHz, respectively.
UR - https://www.scopus.com/pages/publications/85045322104
U2 - 10.1109/ASPDAC.2018.8297336
DO - 10.1109/ASPDAC.2018.8297336
M3 - Conference contribution
AN - SCOPUS:85045322104
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 313
EP - 314
BT - ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Y2 - 22 January 2018 through 25 January 2018
ER -