Low-power class-AB CMOS OTA with high slew-rate

  • Ah Reum Kim
  • , Hyoung Rae Kim
  • , Yoon Suk Park
  • , Yoon Kyung Choi
  • , Bai Sun Kong

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

25 Scopus citations

Abstract

In this paper, a novel low-power class-AB CMOS OTA with high slew-rate is presented. The proposed OTA is based on class-AB input stage using a novel adaptive-biasing. The proposed OTA designed using a standard 0.18-um CMOS technology indicates that rising and falling slew-rates of +4.92 V/μS and -5.04 V/μS with worst-case settling time of 2.1 μS, a voltage gain of 48.97 dB with GBW of 57.27 kHz and phase margin of 78.18 degree were achieved with 10-pF load capacitance and 1.8-V supply voltage. The proposed OTA consumes an overall current of 1.09 μA, and occupies a silicon area of 0.008 mm 2.

Original languageEnglish
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages313-316
Number of pages4
DOIs
StatePublished - 2009
Event2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
Duration: 22 Nov 200924 Nov 2009

Publication series

Name2009 International SoC Design Conference, ISOCC 2009

Conference

Conference2009 International SoC Design Conference, ISOCC 2009
Country/TerritoryKorea, Republic of
CityBusan
Period22/11/0924/11/09

Keywords

  • Adaptive biasing
  • Class-AB OTA
  • CMOS analog circuit
  • Low power
  • Slew rate enhancement

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