Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application

Deeksha Verma; Khuram Shehzad; Sung Jin Kim; Kang Yoon Lee

doi:10.1109/ICEIC49074.2020.9051214

Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application

Deeksha Verma
, Khuram Shehzad
, Sung Jin Kim
, Kang Yoon Lee

Department of Electronic and Electrical Engineering

Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper presents an ultra-low power asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with Wake-up And Sample (WAS) logic. A fully asynchronous operation and WAS logic is proposed to improve the accuracy of the conversion process and to lower the overall power consumption. The proposed Asynchronous SAR ADC achieves an Effective number of bits (ENOB) of 9.757 bit with an input range 0.2 V to 0.8 V at 8 MS/s sampling rate and is implemented in 65 nm CMOS process technology. The current consumption of proposed architecture is 46 μA with 1 V power supply.

Original language	English
Title of host publication	2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728162898
DOIs	https://doi.org/10.1109/ICEIC49074.2020.9051214
State	Published - Jan 2020
Event	2020 International Conference on Electronics, Information, and Communication, ICEIC 2020 - Barcelona, Spain Duration: 19 Jan 2020 → 22 Jan 2020

Publication series

Name	2020 International Conference on Electronics, Information, and Communication, ICEIC 2020

Conference

Conference	2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
Country/Territory	Spain
City	Barcelona
Period	19/01/20 → 22/01/20

Keywords

Asynchronous SAR ADC
Low Power
Wake up and Sample

Access to Document

10.1109/ICEIC49074.2020.9051214

Cite this

Verma, D., Shehzad, K., Kim, S. J., & Lee, K. Y. (2020). Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application. In 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020 Article 9051214 (2020 International Conference on Electronics, Information, and Communication, ICEIC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICEIC49074.2020.9051214

Verma, Deeksha ; Shehzad, Khuram ; Kim, Sung Jin et al. / Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application. 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 International Conference on Electronics, Information, and Communication, ICEIC 2020).

@inproceedings{471403b201444147b5921420bf950080,

title = "Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application",

abstract = "This paper presents an ultra-low power asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with Wake-up And Sample (WAS) logic. A fully asynchronous operation and WAS logic is proposed to improve the accuracy of the conversion process and to lower the overall power consumption. The proposed Asynchronous SAR ADC achieves an Effective number of bits (ENOB) of 9.757 bit with an input range 0.2 V to 0.8 V at 8 MS/s sampling rate and is implemented in 65 nm CMOS process technology. The current consumption of proposed architecture is 46 μA with 1 V power supply.",

keywords = "Asynchronous SAR ADC, Low Power, Wake up and Sample",

author = "Deeksha Verma and Khuram Shehzad and Kim, \{Sung Jin\} and Lee, \{Kang Yoon\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020 ; Conference date: 19-01-2020 Through 22-01-2020",

year = "2020",

month = jan,

doi = "10.1109/ICEIC49074.2020.9051214",

language = "English",

series = "2020 International Conference on Electronics, Information, and Communication, ICEIC 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 International Conference on Electronics, Information, and Communication, ICEIC 2020",

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Verma, D, Shehzad, K, Kim, SJ & Lee, KY 2020, Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application. in 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020., 9051214, 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020, Institute of Electrical and Electronics Engineers Inc., 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020, Barcelona, Spain, 19/01/20. https://doi.org/10.1109/ICEIC49074.2020.9051214

Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application. / Verma, Deeksha; Shehzad, Khuram; Kim, Sung Jin et al.
2020 International Conference on Electronics, Information, and Communication, ICEIC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9051214 (2020 International Conference on Electronics, Information, and Communication, ICEIC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application

AU - Verma, Deeksha

AU - Shehzad, Khuram

AU - Kim, Sung Jin

AU - Lee, Kang Yoon

PY - 2020/1

Y1 - 2020/1

N2 - This paper presents an ultra-low power asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with Wake-up And Sample (WAS) logic. A fully asynchronous operation and WAS logic is proposed to improve the accuracy of the conversion process and to lower the overall power consumption. The proposed Asynchronous SAR ADC achieves an Effective number of bits (ENOB) of 9.757 bit with an input range 0.2 V to 0.8 V at 8 MS/s sampling rate and is implemented in 65 nm CMOS process technology. The current consumption of proposed architecture is 46 μA with 1 V power supply.

AB - This paper presents an ultra-low power asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with Wake-up And Sample (WAS) logic. A fully asynchronous operation and WAS logic is proposed to improve the accuracy of the conversion process and to lower the overall power consumption. The proposed Asynchronous SAR ADC achieves an Effective number of bits (ENOB) of 9.757 bit with an input range 0.2 V to 0.8 V at 8 MS/s sampling rate and is implemented in 65 nm CMOS process technology. The current consumption of proposed architecture is 46 μA with 1 V power supply.

KW - Asynchronous SAR ADC

KW - Low Power

KW - Wake up and Sample

UR - https://www.scopus.com/pages/publications/85083501056

U2 - 10.1109/ICEIC49074.2020.9051214

DO - 10.1109/ICEIC49074.2020.9051214

M3 - Conference contribution

AN - SCOPUS:85083501056

T3 - 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020

BT - 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020

Y2 - 19 January 2020 through 22 January 2020

ER -

Verma D, Shehzad K, Kim SJ, Lee KY. Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application. In 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9051214. (2020 International Conference on Electronics, Information, and Communication, ICEIC 2020). doi: 10.1109/ICEIC49074.2020.9051214

Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application

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