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Low Power 10-bit 100 MSPS Segmented Current Steering DAC with > 78 dB SFDR

  • Venkatesh Kommangunta
  • , Khuram Shehzad
  • , Deeksha Verma
  • , Kang Yoon Lee
  • Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, High static and dynamic performance low power 100 MSPS 10-bit segmented Current Steering DAC (CS-DAC) is presented. This proposed DAC is designed using 130nm CMOS technology for wireless communications. The proposed DAC architecture follows $3+3+4$ segmentations, in which 6 MSB bits are realized with unary DACs, and 4 LSB bits are realized with binary DAC structure. To improve the static and dynamic performance, re-timing latches and Cascoded current cell used, respectively. The proposed DAC, Spurious Free Dynamic Range (SFDR) is > 78 dB for signal frequency up to 33.5 MHz. Integrated Non-Linearity (INL) and Differential Non-Linearity (DNL) of this DAC is 0.25 LSB and 0.0912 LSB, respectively. The current consumption of this DAC is 1.75 mA at 1.2 V supply.

Original languageEnglish
Title of host publication2021 International Conference on Electronics, Information, and Communication, ICEIC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728191614
DOIs
StatePublished - 31 Jan 2021
Event2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 - Jeju, Korea, Republic of
Duration: 31 Jan 20213 Feb 2021

Publication series

Name2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

Conference

Conference2021 International Conference on Electronics, Information, and Communication, ICEIC 2021
Country/TerritoryKorea, Republic of
CityJeju
Period31/01/213/02/21

Keywords

  • Current steering
  • Differential Non-Linearity
  • Integral Non-Linearity
  • Segmented
  • SFDR

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