Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security

Seonho Kim; Changyoun Im; Jongmin Lee; Soyoun Jeong; Jaerok Kim; Yoonmyung Lee

doi:10.1109/ESSCIRC55480.2022.9911394

Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security

Seonho Kim
, Changyoun Im
, Jongmin Lee
, Soyoun Jeong
, Jaerok Kim
, Yoonmyung Lee

Department of Semiconductor Systems Engineering

Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Novel logic-embedded physically unclonable functions (Logic-ePUF) are proposed to significantly reduce design/area cost with minimal modification on standard cells used for semi-custom design flow. By replacing scan flip-flops and buffers in scan chain with proposed flip-flop-ePUF (FF-ePUF) and buffer-ePUF (BUF-ePUF), efficient PUF implementation is enabled without additional readout periphery. The proposed Logic-ePUF not only operates as a standard cell but also as a PUF. To generate secure key, proposed Logic-ePUF operates under PUF mode by comparing the difference of switching voltages (VM) of 1st and 2nd stage inverters. The proposed FF-ePUF and BUF-ePUF are fabricated in 28nm FDSOI process to evaluate effectiveness and performance. The proposed FF-ePUF achieved 178ppm BER through reconfiguration and tilting with 332-447F2/bit area overhead. And the proposed BUF-ePUF reduced 41% of area overhead compared to conventional method.

Original language	English
Title of host publication	ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	521-524
Number of pages	4
ISBN (Electronic)	9781665484947
DOIs	https://doi.org/10.1109/ESSCIRC55480.2022.9911394
State	Published - 2022
Event	48th IEEE European Solid State Circuits Conference, ESSCIRC 2022 - Milan, Italy Duration: 19 Sep 2022 → 22 Sep 2022

Publication series

Name	ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings

Conference

Conference	48th IEEE European Solid State Circuits Conference, ESSCIRC 2022
Country/Territory	Italy
City	Milan
Period	19/09/22 → 22/09/22

Keywords

cost-efficient
hardware security
Internet of Things (IoT)
periphery-free
Physically unclonable function (PUF)
synthesized implementation

Access to Document

10.1109/ESSCIRC55480.2022.9911394

Cite this

Kim, S., Im, C., Lee, J., Jeong, S., Kim, J., & Lee, Y. (2022). Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security. In ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings (pp. 521-524). (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC55480.2022.9911394

Kim, Seonho ; Im, Changyoun ; Lee, Jongmin et al. / Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security. ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 521-524 (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings).

@inproceedings{78d6c02b864b4dd482aad2982114ffcc,

title = "Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security",

abstract = "Novel logic-embedded physically unclonable functions (Logic-ePUF) are proposed to significantly reduce design/area cost with minimal modification on standard cells used for semi-custom design flow. By replacing scan flip-flops and buffers in scan chain with proposed flip-flop-ePUF (FF-ePUF) and buffer-ePUF (BUF-ePUF), efficient PUF implementation is enabled without additional readout periphery. The proposed Logic-ePUF not only operates as a standard cell but also as a PUF. To generate secure key, proposed Logic-ePUF operates under PUF mode by comparing the difference of switching voltages (VM) of 1st and 2nd stage inverters. The proposed FF-ePUF and BUF-ePUF are fabricated in 28nm FDSOI process to evaluate effectiveness and performance. The proposed FF-ePUF achieved 178ppm BER through reconfiguration and tilting with 332-447F2/bit area overhead. And the proposed BUF-ePUF reduced 41\% of area overhead compared to conventional method.",

keywords = "cost-efficient, hardware security, Internet of Things (IoT), periphery-free, Physically unclonable function (PUF), synthesized implementation",

author = "Seonho Kim and Changyoun Im and Jongmin Lee and Soyoun Jeong and Jaerok Kim and Yoonmyung Lee",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022 ; Conference date: 19-09-2022 Through 22-09-2022",

year = "2022",

doi = "10.1109/ESSCIRC55480.2022.9911394",

language = "English",

series = "ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "521--524",

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Kim, S, Im, C, Lee, J, Jeong, S, Kim, J & Lee, Y 2022, Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security. in ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 521-524, 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022, Milan, Italy, 19/09/22. https://doi.org/10.1109/ESSCIRC55480.2022.9911394

Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security. / Kim, Seonho; Im, Changyoun; Lee, Jongmin et al.
ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. p. 521-524 (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security

AU - Kim, Seonho

AU - Im, Changyoun

AU - Lee, Jongmin

AU - Jeong, Soyoun

AU - Kim, Jaerok

AU - Lee, Yoonmyung

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N2 - Novel logic-embedded physically unclonable functions (Logic-ePUF) are proposed to significantly reduce design/area cost with minimal modification on standard cells used for semi-custom design flow. By replacing scan flip-flops and buffers in scan chain with proposed flip-flop-ePUF (FF-ePUF) and buffer-ePUF (BUF-ePUF), efficient PUF implementation is enabled without additional readout periphery. The proposed Logic-ePUF not only operates as a standard cell but also as a PUF. To generate secure key, proposed Logic-ePUF operates under PUF mode by comparing the difference of switching voltages (VM) of 1st and 2nd stage inverters. The proposed FF-ePUF and BUF-ePUF are fabricated in 28nm FDSOI process to evaluate effectiveness and performance. The proposed FF-ePUF achieved 178ppm BER through reconfiguration and tilting with 332-447F2/bit area overhead. And the proposed BUF-ePUF reduced 41% of area overhead compared to conventional method.

AB - Novel logic-embedded physically unclonable functions (Logic-ePUF) are proposed to significantly reduce design/area cost with minimal modification on standard cells used for semi-custom design flow. By replacing scan flip-flops and buffers in scan chain with proposed flip-flop-ePUF (FF-ePUF) and buffer-ePUF (BUF-ePUF), efficient PUF implementation is enabled without additional readout periphery. The proposed Logic-ePUF not only operates as a standard cell but also as a PUF. To generate secure key, proposed Logic-ePUF operates under PUF mode by comparing the difference of switching voltages (VM) of 1st and 2nd stage inverters. The proposed FF-ePUF and BUF-ePUF are fabricated in 28nm FDSOI process to evaluate effectiveness and performance. The proposed FF-ePUF achieved 178ppm BER through reconfiguration and tilting with 332-447F2/bit area overhead. And the proposed BUF-ePUF reduced 41% of area overhead compared to conventional method.

KW - cost-efficient

KW - hardware security

KW - Internet of Things (IoT)

KW - periphery-free

KW - Physically unclonable function (PUF)

KW - synthesized implementation

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M3 - Conference contribution

AN - SCOPUS:85141451091

T3 - ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings

SP - 521

EP - 524

BT - ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022

Y2 - 19 September 2022 through 22 September 2022

ER -

Kim S, Im C, Lee J, Jeong S, Kim J, Lee Y. Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security. In ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2022. p. 521-524. (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings). doi: 10.1109/ESSCIRC55480.2022.9911394

Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security

Abstract

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Conference

Keywords

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