LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage

In memory designs that adopt a full-custom design, accurately predicting the layout size of a circuit block is crucial for reducing design iterations. However, predicting the layout size is challenging due to the complex space sizes caused by wiring and layout-dependent effects between circuit elements. To address the challenge, we propose LayNet, a novel graph neural network model that predicts the layout size by constructing a weighted graph. We convert a circuit into a weighted graph to model the relationships between circuit elements. By applying graph neural networks to the weighted circuit graph, we can accurately predict the layout size. We also propose the edge selection and hierarchical graph learning approaches to reduce memory usage and inference time for large circuit blocks. LayNet achieves state-of-the-art performance on 6300 pairs of circuits and layouts in industrial memory products. Specifically, it significantly reduces the mean absolute percentage error rate by 20.82%∼88.17% for manually-generated layouts and by 7.97%∼73.39% for semiauto-generated layouts, outperforming conventional approaches. Also, the edge selection and hierarchical graph learning approaches reduce memory usage by 140. 85x and 238. 10x for these two types of layouts, respectively, and inference time by 14. 14x and 37. 84x, respectively, while maintaining performance.