Interfacial energy-band engineering for high open-circuit voltage of rear emitter p-type crystalline silicon solar cells

Rear emitter p-type crystalline silicon (c-Si) tunnel oxide passivating contact (P-TOPCon) devices with low-resistivity (≤1 Ω.cm) c-Si wafer and high-conductivity phosphorus doped (n-type) polysilicon passivating contact (n-poly-Si PC) are expected to achieve high built-in potential (V_bi) and thus open-circuit voltage (V_oc). However, the results indicate that the high conductivity of n-poly-Si PC considerably deteriorates the interface passivation quality and lowers the device's V_oc. A crucial factor to consider is that the hole and electron can tunnel and recombine together at the c-Si/n-poly-Si PC contact, resulting in a decrease in the quality of interfacial passivation. To inhibit carrier tunnel diffusion and enable energy band engineering at the interface for achieving high V_oc, a thin intrinsic poly-Si buffer layer (10 nm) is inserted between SiO₂ and n-poly-Si PC. When compared to a device without a buffer, a device with the buffer exhibits a significant improvement in passivation quality and hence V_oc. The device with buffer has a V_oc of 705 mV and an efficiency of 23.5 %, while that without buffer is 681 mV and 22.6 %, respectively. The introduced buffer has little effect on the industrial manufacturing process, but it does significantly enhance V_oc. It has the potential to improve the efficiency of the P-TOPCon devices.